)]}'
{
  "commit": "1d151b8713474e01b9d74b266007b6598ef6db83",
  "tree": "6c256cf82f627e40d620192667310e1296081df0",
  "parents": [
    "6e32d91c543027c9f057b246f4bab41bbc470bcb",
    "632c15f0b75ef314b839980040240bb3982c0c80"
  ],
  "author": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "me@mith.ro",
    "time": "Fri Oct 02 10:01:02 2020 -0700"
  },
  "committer": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "tansell@google.com",
    "time": "Fri Oct 02 10:01:02 2020 -0700"
  },
  "message": "verilog: Fixing usage of cell reserved word.\n\n`cell` is a Verilog reserved word.\n\nSigned-off-by: Tim \u0027mithro\u0027 Ansell \u003ctansell@google.com\u003e\n",
  "tree_diff": []
}