| { |
| "area": 22.3776, |
| "cell_footprint": "sky130_fd_sc_hs__dlclkp", |
| "cell_leakage_power": 0.0, |
| "clock_gating_integrated_cell": "latch_posedge", |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
| "pg_type": "primary_power", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
| "capacitance": 0.01262, |
| "clock": "true", |
| "clock_gate_clock_pin": "true", |
| "direction": "input", |
| "internal_power": { |
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| }, |
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| "min_pulse_width_low": 0.10749, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR" |
| }, |
| "pin,GATE": { |
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| "clock": "false", |
| "clock_gate_enable_pin": "true", |
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| }, |
| "max_transition": 1.0, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
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| }, |
| "related_pin": "CLK", |
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| ] |
| }, |
| "timing_type": "setup_rising" |
| }, |
| { |
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| "related_pin": "CLK", |
| "rise_constraint,sethold_template_rise10x10": { |
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| }, |
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| } |
| ] |
| }, |
| "pin,GCLK": { |
| "clock_gate_out_pin": "true", |
| "direction": "output", |
| "internal_power": { |
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| 0.22887, |
| 0.33773, |
| 0.50159, |
| 0.74806, |
| 1.11654, |
| 1.66769 |
| ], |
| [ |
| 0.01766, |
| 0.05686, |
| 0.07731, |
| 0.10864, |
| 0.15667, |
| 0.2289, |
| 0.33774, |
| 0.50225, |
| 0.74784, |
| 1.11634, |
| 1.66728 |
| ], |
| [ |
| 0.01976, |
| 0.05858, |
| 0.07868, |
| 0.10949, |
| 0.1572, |
| 0.22943, |
| 0.33792, |
| 0.5016, |
| 0.74942, |
| 1.11558, |
| 1.66819 |
| ], |
| [ |
| 0.02241, |
| 0.06145, |
| 0.08096, |
| 0.11159, |
| 0.15831, |
| 0.23013, |
| 0.33864, |
| 0.50305, |
| 0.74689, |
| 1.11579, |
| 1.66944 |
| ], |
| [ |
| 0.02561, |
| 0.06582, |
| 0.08485, |
| 0.11473, |
| 0.16109, |
| 0.23248, |
| 0.34032, |
| 0.50312, |
| 0.74821, |
| 1.11576, |
| 1.6686 |
| ], |
| [ |
| 0.02954, |
| 0.07242, |
| 0.09096, |
| 0.11988, |
| 0.16571, |
| 0.23636, |
| 0.3441, |
| 0.5062, |
| 0.7501, |
| 1.1179, |
| 1.6672 |
| ], |
| [ |
| 0.0346, |
| 0.0815, |
| 0.0999, |
| 0.1283, |
| 0.1736, |
| 0.2435, |
| 0.3507, |
| 0.5124, |
| 0.7561, |
| 1.1206, |
| 1.6714 |
| ] |
| ] |
| }, |
| "timing_sense": "positive_unate" |
| } |
| }, |
| "pin,M0": { |
| "direction": "internal", |
| "internal_node": "M0" |
| }, |
| "statetable,CLK GATE,M0": { |
| "table": [ |
| "L L : - : L", |
| "L H : - : H", |
| "H - : - : N" |
| ] |
| } |
| } |
