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| "next_state": "(D&!SCE) | (SCD&SCE)" |
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| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
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| "voltage_name": "VPWR" |
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| "test_cell": { |
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| "next_state": "D" |
| }, |
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| "pin,D": { |
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| "pin,Q": { |
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| "signal_type": "test_scan_out" |
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| "pin,SCD": { |
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| }, |
| "pin,SCE": { |
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| "signal_type": "test_scan_enable" |
| } |
| } |
| } |
