blob: d95348a8e0b2ccf7a5ece5e70cbd414472ad7bf3 [file] [log] [blame]
{
"description": "Delay latch, inverted enable, single output.",
"file_prefix": "sky130_fd_sc_hs__dlxtn",
"library": "sky130_fd_sc_hs",
"name": "dlxtn",
"parameters": [],
"ports": [
[
"signal",
"Q",
"output",
""
],
[
"signal",
"D",
"input",
""
],
[
"signal",
"GATE_N",
"input",
""
],
[
"power",
"VPWR",
"input",
"supply1"
],
[
"power",
"VGND",
"input",
"supply0"
]
],
"type": "cell",
"verilog_name": "sky130_fd_sc_hs__dlxtn"
}