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  "cell_footprint": "sky130_fd_sc_hs__dlclkp",
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  "clock_gating_integrated_cell": "latch_posedge",
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    "voltage_name": "VGND"
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  "statetable,CLK GATE,M0": {
    "table": [
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      "L H : - : H",
      "H - : - : N"
    ]
  }
}