tree 6281cdf2a48ac99d8e1cd13dda201560e704fee3
parent 1d151b8713474e01b9d74b266007b6598ef6db83
parent a13469d261b5272363c02fef366af22477f2d081
author Tim 'mithro' Ansell <me@mith.ro> 1601658062 -0700
committer Tim 'mithro' Ansell <tansell@google.com> 1601658062 -0700

verilog: Fixing ordering of ports in primitives.

Verilog requires the first signal in a primitive's pin list must be the output.

Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>