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| "cell_footprint": "dlxbn", |
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| "latch IQ, IQ_N": { |
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| { |
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| ], |
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| "voltage_name": "VGND" |
| }, |
| "pg_pin VNB": { |
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| "voltage_name": "VNB" |
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| "pg_pin VPWR": { |
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| "voltage_name": "VPWR" |
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| ] |
| }, |
| "pin GATE_N": { |
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| "clock": "true", |
| "direction": "input", |
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| }, |
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| "min_pulse_width_high": 0.12604, |
| "min_pulse_width_low": 0.12604, |
| "related_ground_pin": "VGND", |
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| }, |
| "pin Q": { |
| "direction": "output", |
| "function": "IQ", |
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