| { |
| "area": 27.1728, |
| "cell_footprint": "dlrtn", |
| "cell_leakage_power": 28.43133, |
| "latch IQ, IQ_N": { |
| "clear": "!RESET_B", |
| "data_in": "D", |
| "enable": "!GATE_N" |
| }, |
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| { |
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| "when": "!RESET_B&!D&!GATE_N" |
| }, |
| { |
| "value": 24.93468, |
| "when": "!RESET_B&!D&GATE_N" |
| }, |
| { |
| "value": 31.53529, |
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| }, |
| { |
| "value": 42.00649, |
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| }, |
| { |
| "value": 21.92962, |
| "when": "RESET_B&!D&!GATE_N" |
| }, |
| { |
| "value": 21.50247, |
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| }, |
| { |
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| }, |
| { |
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| } |
| ], |
| "pg_pin VGND": { |
| "pg_type": "primary_ground", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin VNB": { |
| "pg_type": "primary_ground", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin VPB": { |
| "pg_type": "primary_power", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin VPWR": { |
| "pg_type": "primary_power", |
| "voltage_name": "VPWR" |
| }, |
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| "clock": "false", |
| "direction": "input", |
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| }, |
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| ] |
| }, |
| "pin GATE_N": { |
| "capacitance": 0.00264, |
| "clock": "true", |
| "direction": "input", |
| "internal_power": { |
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| }, |
| "max_transition": 1.0, |
| "min_pulse_width_high": 0.12995, |
| "min_pulse_width_low": 0.12995, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR" |
| }, |
| "pin Q": { |
| "direction": "output", |
| "function": "IQ", |
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| }, |
| "timing_type": "recovery_rising" |
| }, |
| { |
| "related_pin": "GATE_N", |
| "rise_constraint rr_template10x10": { |
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| }, |
| "timing_type": "removal_rising" |
| }, |
| { |
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| }, |
| "related_pin": "RESET_B", |
| "rise_constraint pulse_width_template13": { |
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| 2.11117, |
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| ] |
| }, |
| "timing_type": "min_pulse_width" |
| } |
| ] |
| } |
| } |
