| commit | d1e4650c36a3af1b266103a9aca26a0ec004cf53 | [log] [tgz] |
|---|---|---|
| author | Tim 'mithro' Ansell <me@mith.ro> | Fri Oct 02 10:01:02 2020 -0700 |
| committer | Tim 'mithro' Ansell <tansell@google.com> | Fri Oct 02 10:01:02 2020 -0700 |
| tree | 6281cdf2a48ac99d8e1cd13dda201560e704fee3 | |
| parent | 1d151b8713474e01b9d74b266007b6598ef6db83 [diff] | |
| parent | a13469d261b5272363c02fef366af22477f2d081 [diff] |
verilog: Fixing ordering of ports in primitives. Verilog requires the first signal in a primitive's pin list must be the output. Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>