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| "next_state": "(D&!SCE) | (SCD&SCE)" |
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| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
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| "physical_connection": "device_layer", |
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| "voltage_name": "VPWR" |
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| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
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| { |
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| "timing_type": "removal_rising" |
| }, |
| { |
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| "related_pin": "RESET_B", |
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| }, |
| "timing_type": "min_pulse_width" |
| } |
| ] |
| }, |
| "pin,SCD": { |
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| "clock": "false", |
| "direction": "input", |
| "internal_power": { |
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| } |
| }, |
| "max_transition": 1.0, |
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| 0.55664, |
| 0.53906 |
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| ] |
| }, |
| "timing_type": "setup_rising" |
| }, |
| { |
| "fall_constraint,sethold_template_fall10x10": { |
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| 0.03125, |
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| }, |
| "related_pin": "CLK", |
| "rise_constraint,sethold_template_rise10x10": { |
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| ] |
| ] |
| }, |
| "timing_type": "hold_rising" |
| } |
| ] |
| }, |
| "test_cell": { |
| "ff,IQ,IQ_N": { |
| "clear": "!RESET_B", |
| "clocked_on": "CLK", |
| "next_state": "D" |
| }, |
| "pin,CLK": { |
| "direction": "input" |
| }, |
| "pin,D": { |
| "direction": "input" |
| }, |
| "pin,Q": { |
| "direction": "output", |
| "function": "IQ", |
| "signal_type": "test_scan_out" |
| }, |
| "pin,RESET_B": { |
| "direction": "input" |
| }, |
| "pin,SCD": { |
| "direction": "input", |
| "signal_type": "test_scan_in" |
| }, |
| "pin,SCE": { |
| "direction": "input", |
| "signal_type": "test_scan_enable" |
| } |
| } |
| } |
