| { |
| "area": 28.7712, |
| "cell_footprint": "sky130_fd_sc_hs__dlclkp", |
| "cell_leakage_power": 0.0, |
| "clock_gating_integrated_cell": "latch_posedge", |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
| "pg_type": "primary_power", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
| "capacitance": 0.01252, |
| "clock": "true", |
| "clock_gate_clock_pin": "true", |
| "direction": "input", |
| "internal_power": { |
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| }, |
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| "min_pulse_width_low": 0.40925, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR" |
| }, |
| "pin,GATE": { |
| "capacitance": 0.00234, |
| "clock": "false", |
| "clock_gate_enable_pin": "true", |
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| } |
| }, |
| "max_transition": 1.0, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "timing": [ |
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| }, |
| "related_pin": "CLK", |
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| ] |
| }, |
| "timing_type": "setup_rising" |
| }, |
| { |
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| }, |
| "related_pin": "CLK", |
| "rise_constraint,sethold_template_rise10x10": { |
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| }, |
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| } |
| ] |
| }, |
| "pin,GCLK": { |
| "clock_gate_out_pin": "true", |
| "direction": "output", |
| "internal_power": { |
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| 0.04281, |
| 0.0958, |
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| 0.1611, |
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| 0.31142, |
| 0.44948, |
| 0.65827, |
| 0.97117, |
| 1.44124, |
| 2.14339 |
| ], |
| [ |
| 0.04281, |
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| 0.12172, |
| 0.16102, |
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| 0.31176, |
| 0.44958, |
| 0.65834, |
| 0.97141, |
| 1.43846, |
| 2.1438 |
| ], |
| [ |
| 0.04279, |
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| 0.161, |
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| 0.31188, |
| 0.44981, |
| 0.65786, |
| 0.97238, |
| 1.44008, |
| 2.1459 |
| ], |
| [ |
| 0.0441, |
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| 0.1221, |
| 0.16129, |
| 0.22076, |
| 0.31194, |
| 0.44992, |
| 0.65784, |
| 0.97131, |
| 1.44, |
| 2.1449 |
| ], |
| [ |
| 0.04683, |
| 0.099, |
| 0.1244, |
| 0.163, |
| 0.222, |
| 0.3126, |
| 0.4501, |
| 0.6577, |
| 0.9708, |
| 1.4412, |
| 2.1438 |
| ], |
| [ |
| 0.0506, |
| 0.1025, |
| 0.1279, |
| 0.1661, |
| 0.2245, |
| 0.3144, |
| 0.4516, |
| 0.6593, |
| 0.9704, |
| 1.4419, |
| 2.1464 |
| ], |
| [ |
| 0.0559, |
| 0.1075, |
| 0.1324, |
| 0.1699, |
| 0.2278, |
| 0.3172, |
| 0.453, |
| 0.6594, |
| 0.9718, |
| 1.4415, |
| 2.1457 |
| ] |
| ] |
| }, |
| "timing_sense": "positive_unate" |
| } |
| }, |
| "pin,M0": { |
| "direction": "internal", |
| "internal_node": "M0" |
| }, |
| "statetable,CLK GATE,M0": { |
| "table": [ |
| "L L : - : L", |
| "L H : - : H", |
| "H - : - : N" |
| ] |
| } |
| } |
