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| "cell_footprint": "sky130_fd_sc_hs__dlclkp", |
| "cell_leakage_power": 0.0, |
| "clock_gating_integrated_cell": "latch_posedge", |
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| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
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| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
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| "physical_connection": "device_layer", |
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| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
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| "clock": "true", |
| "clock_gate_clock_pin": "true", |
| "direction": "input", |
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| }, |
| "pin,GCLK": { |
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| 0.01499, |
| 0.06304, |
| 0.08808, |
| 0.12626, |
| 0.18395, |
| 0.27088, |
| 0.40202, |
| 0.59795, |
| 0.89337, |
| 1.33583, |
| 1.99819 |
| ], |
| [ |
| 0.01679, |
| 0.06359, |
| 0.08868, |
| 0.12668, |
| 0.18441, |
| 0.27163, |
| 0.40178, |
| 0.59899, |
| 0.89339, |
| 1.3342, |
| 1.99967 |
| ], |
| [ |
| 0.01926, |
| 0.06461, |
| 0.08926, |
| 0.12713, |
| 0.18473, |
| 0.27145, |
| 0.40316, |
| 0.59845, |
| 0.89233, |
| 1.33441, |
| 1.99926 |
| ], |
| [ |
| 0.02267, |
| 0.06656, |
| 0.09049, |
| 0.12793, |
| 0.18535, |
| 0.27207, |
| 0.40266, |
| 0.59953, |
| 0.89267, |
| 1.33589, |
| 1.99648 |
| ], |
| [ |
| 0.02714, |
| 0.07019, |
| 0.09329, |
| 0.12979, |
| 0.18639, |
| 0.27263, |
| 0.40301, |
| 0.5992, |
| 0.89441, |
| 1.33505, |
| 2.0016 |
| ], |
| [ |
| 0.03283, |
| 0.07666, |
| 0.09854, |
| 0.13385, |
| 0.18956, |
| 0.27567, |
| 0.40415, |
| 0.6016, |
| 0.8939, |
| 1.3353, |
| 1.9992 |
| ], |
| [ |
| 0.04, |
| 0.0874, |
| 0.1081, |
| 0.1416, |
| 0.1955, |
| 0.2798, |
| 0.4087, |
| 0.6029, |
| 0.8964, |
| 1.3374, |
| 1.9995 |
| ] |
| ] |
| }, |
| "timing_sense": "positive_unate" |
| } |
| }, |
| "pin,M0": { |
| "direction": "internal", |
| "internal_node": "M0" |
| }, |
| "statetable,CLK GATE,M0": { |
| "table": [ |
| "L L : - : L", |
| "L H : - : H", |
| "H - : - : N" |
| ] |
| } |
| } |
