blob: 30d6d6fe1b27d9b665f91a41faf71d700039306f [file] [log] [blame]
{
"description": "Clock Delay Inverter 5-stage 0.15um length inner stage gate.",
"file_prefix": "sky130_fd_sc_hs__clkdlyinv5sd1",
"library": "sky130_fd_sc_hs",
"name": "clkdlyinv5sd1",
"parameters": [],
"ports": [
[
"signal",
"Y",
"output",
""
],
[
"signal",
"A",
"input",
""
],
[
"power",
"VPWR",
"input",
"supply1"
],
[
"power",
"VGND",
"input",
"supply0"
]
],
"type": "cell",
"verilog_name": "sky130_fd_sc_hs__clkdlyinv5sd1"
}