| { |
| "area": 31.968, |
| "cell_footprint": "sky130_fd_sc_hs__sdlclkp", |
| "cell_leakage_power": 13377.44712, |
| "clock_gating_integrated_cell": "latch_posedge_precontrol", |
| "leakage_power": [ |
| { |
| "value": 15724.84692, |
| "when": "!GATE&!SCE&!CLK" |
| }, |
| { |
| "value": 15232.79033, |
| "when": "!GATE&!SCE&CLK" |
| }, |
| { |
| "value": 13834.31486, |
| "when": "!GATE&SCE&!CLK" |
| }, |
| { |
| "value": 11245.28455, |
| "when": "!GATE&SCE&CLK" |
| }, |
| { |
| "value": 15752.16997, |
| "when": "GATE&!SCE&!CLK" |
| }, |
| { |
| "value": 13169.77018, |
| "when": "GATE&!SCE&CLK" |
| }, |
| { |
| "value": 12324.42278, |
| "when": "GATE&SCE&!CLK" |
| }, |
| { |
| "value": 9735.97739, |
| "when": "GATE&SCE&CLK" |
| } |
| ], |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
| "pg_type": "primary_power", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
| "capacitance": 0.01266, |
| "clock": "true", |
| "clock_gate_clock_pin": "true", |
| "direction": "input", |
| "internal_power": { |
| "fall_power,hidden_pwr_template13": { |
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| 0.01735, |
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| ] |
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| }, |
| "max_transition": 1.0, |
| "min_pulse_width_high": 0.08698, |
| "min_pulse_width_low": 0.08698, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR" |
| }, |
| "pin,GATE": { |
| "capacitance": 0.00237, |
| "clock": "false", |
| "clock_gate_enable_pin": "true", |
| "direction": "input", |
| "internal_power": { |
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| ] |
| } |
| }, |
| "max_transition": 1.0, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "timing": [ |
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| [ |
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| 0.39342, |
| 0.411, |
| 0.42858, |
| 0.44616, |
| 0.46374 |
| ] |
| ] |
| }, |
| "related_pin": "CLK", |
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| 0.03125, |
| 0.0625, |
| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
| 1.25, |
| 1.5 |
| ], |
| "index_2": [ |
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| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
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| ], |
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| [ |
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| 0.12975, |
| 0.16198, |
| 0.1942, |
| 0.22643 |
| ] |
| ] |
| }, |
| "timing_type": "setup_rising" |
| }, |
| { |
| "fall_constraint,sethold_template_fall10x10": { |
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| 0.01, |
| 0.03125, |
| 0.0625, |
| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
| 1.25, |
| 1.5 |
| ], |
| "index_2": [ |
| 0.01, |
| 0.03125, |
| 0.0625, |
| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
| 1.25, |
| 1.5 |
| ], |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| -0.32142, |
| -0.339, |
| -0.35658, |
| -0.37416 |
| ] |
| ] |
| }, |
| "related_pin": "CLK", |
| "rise_constraint,sethold_template_rise10x10": { |
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| 0.01, |
| 0.03125, |
| 0.0625, |
| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
| 1.25, |
| 1.5 |
| ], |
| "index_2": [ |
| 0.01, |
| 0.03125, |
| 0.0625, |
| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
| 1.25, |
| 1.5 |
| ], |
| "values": [ |
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| ], |
| [ |
| 0.00377, |
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| 0.0067, |
| 0.0067, |
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| [ |
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| 0.00084, |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
| 0.00963, |
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| [ |
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| -0.10755, |
| -0.13978 |
| ] |
| ] |
| }, |
| "timing_type": "hold_rising" |
| } |
| ] |
| }, |
| "pin,GCLK": { |
| "clock_gate_out_pin": "true", |
| "direction": "output", |
| "internal_power": { |
| "fall_power,pwr_template13x14": { |
| "index_1": [ |
| 0.01, |
| 0.01735, |
| 0.02602, |
| 0.03903, |
| 0.05855, |
| 0.08782, |
| 0.13172, |
| 0.19757, |
| 0.29634, |
| 0.44449, |
| 0.6667, |
| 1.0, |
| 1.5 |
| ], |
| "index_2": [ |
| 0.0, |
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| 0.01141, |
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| 0.02566, |
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| 0.19482, |
| 0.29223, |
| 0.43835, |
| 0.65753, |
| 0.9863 |
| ], |
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| 0.12308, |
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| [ |
| 0.16488, |
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| 0.07825, |
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| [ |
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| [ |
| 0.16657, |
| 0.14661, |
| 0.13758, |
| 0.12463, |
| 0.10618, |
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| "statetable,CLK GATE SCE,M0": { |
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| } |
