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| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
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| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
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| "voltage_name": "VPWR" |
| }, |
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| "clock_gate_clock_pin": "true", |
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| 0.5002, |
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| 1.11548, |
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| [ |
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| 0.50134, |
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| [ |
| 0.0279, |
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| 0.08915, |
| 0.11811, |
| 0.16422, |
| 0.23528, |
| 0.34274, |
| 0.5052, |
| 0.7487, |
| 1.116, |
| 1.6693 |
| ], |
| [ |
| 0.0338, |
| 0.082, |
| 0.1, |
| 0.128, |
| 0.1726, |
| 0.2429, |
| 0.3501, |
| 0.5123, |
| 0.7546, |
| 1.1209, |
| 1.6709 |
| ] |
| ] |
| }, |
| "timing_sense": "positive_unate" |
| } |
| }, |
| "pin,M0": { |
| "direction": "internal", |
| "internal_node": "M0" |
| }, |
| "statetable,CLK GATE,M0": { |
| "table": [ |
| "L L : - : L", |
| "L H : - : H", |
| "H - : - : N" |
| ] |
| } |
| } |
