{
 "description": "2-input AND into all inputs of 3-input OR.",
 "equation": "X = ((A1 & A2) | (B1 & B2) | (C1 & C2))",
 "file_prefix": "sky130_fd_sc_hs__a222o",
 "library": "sky130_fd_sc_hs",
 "name": "a222o",
 "parameters": [],
 "ports": [
  [
   "signal",
   "X",
   "output",
   ""
  ],
  [
   "signal",
   "A1",
   "input",
   ""
  ],
  [
   "signal",
   "A2",
   "input",
   ""
  ],
  [
   "signal",
   "B1",
   "input",
   ""
  ],
  [
   "signal",
   "B2",
   "input",
   ""
  ],
  [
   "signal",
   "C1",
   "input",
   ""
  ],
  [
   "signal",
   "C2",
   "input",
   ""
  ],
  [
   "power",
   "VPWR",
   "input",
   "supply1"
  ],
  [
   "power",
   "VGND",
   "input",
   "supply0"
  ]
 ],
 "type": "cell",
 "verilog_name": "sky130_fd_sc_hs__a222o"
}