tree 6898c5145692c31665ab0510e856dc9fede33079
parent 3c7f2248f1cc7db237a8cb98e6dbeece900e3793
author Tim 'mithro' Ansell <me@mith.ro> 1601658062 -0700
committer Tim 'mithro' Ansell <tansell@google.com> 1601658062 -0700

verilog: Fixing usage of cell reserved word.

`cell` is a Verilog reserved word.

Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>