| commit | a13469d261b5272363c02fef366af22477f2d081 | [log] [tgz] |
|---|---|---|
| author | Tim 'mithro' Ansell <me@mith.ro> | Fri Oct 02 10:01:02 2020 -0700 |
| committer | Tim 'mithro' Ansell <tansell@google.com> | Fri Oct 02 10:01:02 2020 -0700 |
| tree | 8e01662a9e2d856dd1f1e0090d8f05f6f39a0981 | |
| parent | 632c15f0b75ef314b839980040240bb3982c0c80 [diff] |
verilog: Fixing ordering of ports in primitives. Verilog requires the first signal in a primitive's pin list must be the output. Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>