verilog: Fixing ordering of ports in primitives.

Verilog requires the first signal in a primitive's pin list must be the output.

Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>
4 files changed
tree: 8e01662a9e2d856dd1f1e0090d8f05f6f39a0981
  1. .gitignore
  2. LICENSE
  3. README.rst
  4. cells/
  5. models/
  6. tech/
  7. timing/