/**
 * Copyright 2020 The SkyWater PDK Authors
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     https://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

`ifndef SKY130_FD_SC_HS__UDP_DFF_NSR_PP_PG_V
`define SKY130_FD_SC_HS__UDP_DFF_NSR_PP_PG_V

/**
 * udp_dff$NSR_pp$PG: Negative edge triggered D flip-flop
 *                    (Q output UDP) with both active high reset and
 *                    set (set dominate). Includes VPWR and VGND power
 *                    pins.
 *
 * Verilog primitive definition.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none

`ifdef NO_PRIMITIVES
`include "./sky130_fd_sc_hs__udp_dff_nsr_pp_pg.blackbox.v"
`else
primitive sky130_fd_sc_hs__udp_dff$NSR_pp$PG (
    Q    ,
    SET  ,
    RESET,
    CLK_N,
    D    ,
    VPWR ,
    VGND
);

    output Q    ;
    input  SET  ;
    input  RESET;
    input  CLK_N;
    input  D    ;
    input  VPWR ;
    input  VGND ;

    reg Q;

    table
     // SET RESET CLK_N  D  VPWR VGND :  Qt : Qt+1
         0    1     ?    ?   1    0   :  ?  :  0    ; // Asserting reset
         0    *     ?    ?   1    0   :  0  :  0    ; // Changing reset
         1    ?     ?    ?   1    0   :  ?  :  1    ; // Asserting set (dominates reset)
         *    0     ?    ?   1    0   :  1  :  1    ; // Changing set
         0    ?    (01)  0   1    0   :  ?  :  0    ; // rising clock
         ?    0    (01)  1   1    0   :  ?  :  1    ; // rising clock
         0    ?     p    0   1    0   :  0  :  0    ; // potential rising clock
         ?    0     p    1   1    0   :  1  :  1    ; // potential rising clock
         0    0     n    ?   1    0   :  ?  :  -    ; // Clock falling register output does not change
         0    0     ?    *   1    0   :  ?  :  -    ; // Changing Data
         ?    ?     ?    ?   *    0   :  ?  :  x    ; // any change on vpwr
         ?    ?     ?    ?   ?    *   :  ?  :  x    ; // any change on vgnd
    endtable
endprimitive
`endif // NO_PRIMITIVES

`default_nettype wire
`endif  // SKY130_FD_SC_HS__UDP_DFF_NSR_PP_PG_V