{ | |
"description": "Full adder.", | |
"file_prefix": "sky130_fd_sc_hs__fa", | |
"library": "sky130_fd_sc_hs", | |
"name": "fa", | |
"parameters": [], | |
"ports": [ | |
[ | |
"signal", | |
"COUT", | |
"output", | |
"" | |
], | |
[ | |
"signal", | |
"SUM", | |
"output", | |
"" | |
], | |
[ | |
"signal", | |
"A", | |
"input", | |
"" | |
], | |
[ | |
"signal", | |
"B", | |
"input", | |
"" | |
], | |
[ | |
"signal", | |
"CIN", | |
"input", | |
"" | |
], | |
[ | |
"power", | |
"VPWR", | |
"input", | |
"supply1" | |
], | |
[ | |
"power", | |
"VGND", | |
"input", | |
"supply0" | |
] | |
], | |
"type": "cell", | |
"verilog_name": "sky130_fd_sc_hs__fa" | |
} |