| { |
| "area": 27.1728, |
| "cell_footprint": "sky130_fd_sc_hs__dfxtp", |
| "cell_leakage_power": 2239.34478, |
| "ff,IQ,IQ_N": { |
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| "next_state": "D" |
| }, |
| "leakage_power": [ |
| { |
| "value": 1849.62378, |
| "when": "!D&!CLK" |
| }, |
| { |
| "value": 2156.3409, |
| "when": "!D&CLK" |
| }, |
| { |
| "value": 2774.9102, |
| "when": "D&!CLK" |
| }, |
| { |
| "value": 2176.50423, |
| "when": "D&CLK" |
| } |
| ], |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
| "pg_type": "primary_power", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
| "capacitance": 0.0031, |
| "clock": "true", |
| "direction": "input", |
| "internal_power": { |
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| }, |
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| "min_pulse_width_low": 0.2901, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR" |
| }, |
| "pin,D": { |
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| "clock": "false", |
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| ] |
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| 0.00979, |
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| 0.0114 |
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| }, |
| "max_transition": 1.0, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
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| 0.54688, |
| 0.51562 |
| ] |
| ] |
| }, |
| "related_pin": "CLK", |
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| 0.03125, |
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| 0.75, |
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| 0.25781, |
| 0.23828 |
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| ] |
| }, |
| "timing_type": "setup_rising" |
| }, |
| { |
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| 0.75, |
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| ] |
| }, |
| "related_pin": "CLK", |
| "rise_constraint,sethold_template_rise10x10": { |
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| 0.75, |
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| 0.15624, |
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| 1e-05, |
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| ] |
| }, |
| "timing_type": "hold_rising" |
| } |
| ] |
| }, |
| "pin,Q": { |
| "direction": "output", |
| "function": "IQ", |
| "internal_power": { |
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