)]}'
{
  "commit": "2a82aa593da417e5b757736ef67ddd5d37a80ace",
  "tree": "565caf8648208a0ab399c244cb1fd6fd7425cf48",
  "parents": [
    "d672c39737b5ca3963c3b9e64dd9d6bcbf929ec9",
    "a145d4373b1449b5bee7521bea09c6e62db088f4"
  ],
  "author": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "me@mith.ro",
    "time": "Wed Oct 28 20:05:43 2020 -0700"
  },
  "committer": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "tansell@google.com",
    "time": "Wed Oct 28 20:05:43 2020 -0700"
  },
  "message": "verilog: Fixing power pins usage in non-powerpin mode.\n\nPreviously even when `USE_POWER_PIN` was not defined, the drive strength\nwrappers where still defining the power pins as ports.\n\nFixes https://github.com/google/skywater-pdk/issues/181\n\nSigned-off-by: Tim \u0027mithro\u0027 Ansell \u003ctansell@google.com\u003e\n",
  "tree_diff": []
}