blob: 0b3ffca17ac0e31510297d58bde84d9142db1472 [file] [log] [blame]
{
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"clock_gating_integrated_cell": "latch_posedge_precontrol",
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"voltage_name": "VGND"
},
"pg_pin VNB": {
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"voltage_name": "VNB"
},
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},
"pg_pin VPWR": {
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"related_ground_pin": "VGND",
"related_power_pin": "VPWR",
"state_function": "(CLK*M0)",
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-0.00118
],
[
-0.00704,
-0.00118,
0.00468,
0.01054,
0.01347,
0.0164,
0.01054,
0.00468,
-0.00411,
-0.0129
],
[
-0.02755,
-0.02169,
-0.01583,
-0.00997,
-0.00704,
-0.00411,
-0.00997,
-0.01583,
-0.02462,
-0.03341
],
[
-0.05978,
-0.05392,
-0.04806,
-0.0422,
-0.03927,
-0.03634,
-0.03927,
-0.04806,
-0.05392,
-0.06564
],
[
-0.10372,
-0.09493,
-0.08907,
-0.08321,
-0.07735,
-0.07735,
-0.08028,
-0.08614,
-0.09493,
-0.10372
],
[
-0.13009,
-0.12423,
-0.11837,
-0.10958,
-0.10665,
-0.10372,
-0.10665,
-0.11251,
-0.1213,
-0.13009
],
[
-0.1506,
-0.14474,
-0.13888,
-0.13009,
-0.12423,
-0.12423,
-0.12716,
-0.13302,
-0.14181,
-0.1506
],
[
-0.16525,
-0.15939,
-0.15353,
-0.14767,
-0.14181,
-0.13888,
-0.14181,
-0.14767,
-0.15646,
-0.16525
],
[
-0.17989,
-0.1711,
-0.16525,
-0.15939,
-0.15353,
-0.1506,
-0.15646,
-0.16232,
-0.16817,
-0.17696
]
]
},
"timing_type": "hold_rising"
}
]
},
"statetable \"CLK GATE SCE\",\"M0\"": {
"table": "L L L : - : L ,L L H : - : H ,L H L : - : H ,L H H : - : H ,H - - : - : N"
}
}