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foss-eda-tools / skywater-pdk / libs / sky130_fd_sc_hs / 2347567ca9bbf4a646a7987c20fe4759ef0bd091 / . / cells / dlclkp / sky130_fd_sc_hs__dlclkp_4__ss_n40C_1v60_ccsnoise.lib.json
blob: a9df81eac8224c0b87889792e5bb58adc45f5bbf [file] [log] [blame]
{
"area": 28.7712,
"cell_footprint": "dlclkp",
"cell_leakage_power": 1040.5404,
"clock_gating_integrated_cell": "latch_posedge",
"leakage_power": [
{
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"when": "!CLK&!GATE"
},
{
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},
{
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},
{
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}
],
"pg_pin VGND": {
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"voltage_name": "VGND"
},
"pg_pin VNB": {
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"voltage_name": "VNB"
},
"pg_pin VPB": {
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"voltage_name": "VPB"
},
"pg_pin VPWR": {
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"voltage_name": "VPWR"
},
"pin CLK": {
"capacitance": 0.01269,
"ccsn_first_stage": {
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},
"is_inverting": "true",
"is_needed": "true",
"miller_cap_fall": 0.000532,
"miller_cap_rise": 0.000632,
"output_voltage_fall": {
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