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| "cell_leakage_power": 0.0, |
| "clock_gating_integrated_cell": "latch_posedge", |
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| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
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| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
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| "physical_connection": "device_layer", |
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| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
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| "clock": "true", |
| "clock_gate_clock_pin": "true", |
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| ] |
| }, |
| "pin,GCLK": { |
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| 0.12645, |
| 0.1832, |
| 0.26851, |
| 0.39686, |
| 0.58986, |
| 0.87717, |
| 1.31155, |
| 1.96726 |
| ], |
| [ |
| 0.01951, |
| 0.06598, |
| 0.09021, |
| 0.12734, |
| 0.18397, |
| 0.26903, |
| 0.39765, |
| 0.58999, |
| 0.87853, |
| 1.31201, |
| 1.95984 |
| ], |
| [ |
| 0.02177, |
| 0.06729, |
| 0.09133, |
| 0.12804, |
| 0.18418, |
| 0.26973, |
| 0.3974, |
| 0.58982, |
| 0.87877, |
| 1.3139, |
| 1.96251 |
| ], |
| [ |
| 0.02493, |
| 0.06936, |
| 0.09268, |
| 0.12905, |
| 0.18497, |
| 0.26999, |
| 0.39771, |
| 0.58976, |
| 0.8798, |
| 1.31417, |
| 1.96581 |
| ], |
| [ |
| 0.02909, |
| 0.07299, |
| 0.09563, |
| 0.1315, |
| 0.18635, |
| 0.27085, |
| 0.39831, |
| 0.59036, |
| 0.87996, |
| 1.3124, |
| 1.9632 |
| ], |
| [ |
| 0.03429, |
| 0.07894, |
| 0.10067, |
| 0.13523, |
| 0.1898, |
| 0.2731, |
| 0.3998, |
| 0.5914, |
| 0.879, |
| 1.3153, |
| 1.962 |
| ], |
| [ |
| 0.0407, |
| 0.0882, |
| 0.1091, |
| 0.1421, |
| 0.1951, |
| 0.2782, |
| 0.4041, |
| 0.5953, |
| 0.8818, |
| 1.3121, |
| 1.9609 |
| ] |
| ] |
| }, |
| "timing_sense": "positive_unate" |
| } |
| }, |
| "pin,M0": { |
| "direction": "internal", |
| "internal_node": "M0" |
| }, |
| "statetable,CLK GATE,M0": { |
| "table": [ |
| "L L : - : L", |
| "L H : - : H", |
| "H - : - : N" |
| ] |
| } |
| } |
