| { |
| "area": 22.3776, |
| "cell_footprint": "sky130_fd_sc_hs__dlclkp", |
| "cell_leakage_power": 9952.06387, |
| "clock_gating_integrated_cell": "latch_posedge", |
| "leakage_power": [ |
| { |
| "value": 10835.97247, |
| "when": "!GATE&!CLK" |
| }, |
| { |
| "value": 9568.64317, |
| "when": "!GATE&CLK" |
| }, |
| { |
| "value": 9295.29044, |
| "when": "GATE&!CLK" |
| }, |
| { |
| "value": 10108.34941, |
| "when": "GATE&CLK" |
| } |
| ], |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
| "pg_type": "primary_power", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
| "capacitance": 0.01262, |
| "clock": "true", |
| "clock_gate_clock_pin": "true", |
| "direction": "input", |
| "internal_power": { |
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| }, |
| "max_transition": 1.0, |
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| "min_pulse_width_low": 0.07819, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR" |
| }, |
| "pin,GATE": { |
| "capacitance": 0.00277, |
| "clock": "false", |
| "clock_gate_enable_pin": "true", |
| "direction": "input", |
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| ] |
| } |
| }, |
| "max_transition": 1.0, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "timing": [ |
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| 0.28502, |
| 0.29088, |
| 0.29967, |
| 0.31432, |
| 0.32604 |
| ] |
| ] |
| }, |
| "related_pin": "CLK", |
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| 0.03125, |
| 0.0625, |
| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
| 1.25, |
| 1.5 |
| ], |
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| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
| 1.25, |
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| ], |
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| [ |
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| 0.15905, |
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| 0.08581, |
| 0.1151, |
| 0.14733, |
| 0.17663 |
| ] |
| ] |
| }, |
| "timing_type": "setup_rising" |
| }, |
| { |
| "fall_constraint,sethold_template_fall10x10": { |
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| 0.01, |
| 0.03125, |
| 0.0625, |
| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
| 1.25, |
| 1.5 |
| ], |
| "index_2": [ |
| 0.01, |
| 0.03125, |
| 0.0625, |
| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
| 1.25, |
| 1.5 |
| ], |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| -0.1222, |
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| [ |
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| [ |
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| -0.20423, |
| -0.21302, |
| -0.22767, |
| -0.23939 |
| ] |
| ] |
| }, |
| "related_pin": "CLK", |
| "rise_constraint,sethold_template_rise10x10": { |
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| 0.01, |
| 0.03125, |
| 0.0625, |
| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
| 1.25, |
| 1.5 |
| ], |
| "index_2": [ |
| 0.01, |
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| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
| 1.25, |
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| ], |
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| [ |
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| 0.00084, |
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| [ |
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| [ |
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| [ |
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| 0.00084, |
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| -0.08998 |
| ] |
| ] |
| }, |
| "timing_type": "hold_rising" |
| } |
| ] |
| }, |
| "pin,GCLK": { |
| "clock_gate_out_pin": "true", |
| "direction": "output", |
| "internal_power": { |
| "fall_power,pwr_template13x11": { |
| "index_1": [ |
| 0.01, |
| 0.01735, |
| 0.02602, |
| 0.03903, |
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| 0.13172, |
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| 0.29634, |
| 0.44449, |
| 0.6667, |
| 1.0, |
| 1.5 |
| ], |
| "index_2": [ |
| 0.0, |
| 0.00795, |
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| 0.02683, |
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| 0.20375, |
| 0.30563 |
| ], |
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| 1.23318, |
| 1.14686, |
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| [ |
| 1.40556, |
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| 1.38214, |
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| 1.28976, |
| 1.23223, |
| 1.14589, |
| 1.0164, |
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| 1.14405, |
| 1.01456, |
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| [ |
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| 1.22891, |
| 1.14257, |
| 1.01308, |
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| [ |
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| [ |
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| 0.47007, |
| 0.6824, |
| 1.0032, |
| 1.4887 |
| ], |
| [ |
| 0.0504, |
| 0.0898, |
| 0.1086, |
| 0.1364, |
| 0.1793, |
| 0.2443, |
| 0.3415, |
| 0.4872, |
| 0.705, |
| 1.0223, |
| 1.5018 |
| ] |
| ] |
| }, |
| "timing_sense": "positive_unate" |
| } |
| }, |
| "pin,M0": { |
| "direction": "internal", |
| "internal_node": "M0" |
| }, |
| "statetable,CLK GATE,M0": { |
| "table": [ |
| "L L : - : L", |
| "L H : - : H", |
| "H - : - : N" |
| ] |
| } |
| } |
