)]}'
{
  "commit": "1dc32e3940b584a6ef4356aa7c4131920d991bf3",
  "tree": "e3d5d3b4a8718051e3352a2ff9333a7aae290d1d",
  "parents": [
    "75bfa306ef943736f52bb1c2be997517fe110068",
    "0934c6ec44836066ab74669eac995ff803ddb819"
  ],
  "author": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "me@mith.ro",
    "time": "Fri Oct 02 10:01:02 2020 -0700"
  },
  "committer": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "tansell@google.com",
    "time": "Fri Oct 02 10:01:02 2020 -0700"
  },
  "message": "verilog: Fixing usage of cell reserved word.\n\n`cell` is a Verilog reserved word.\n\nSigned-off-by: Tim \u0027mithro\u0027 Ansell \u003ctansell@google.com\u003e\n",
  "tree_diff": []
}