{
  "area": 12.512,
  "cell_footprint": "or3b",
  "cell_leakage_power": 0.0,
  "pg_pin VGND": {
    "pg_type": "primary_ground",
    "related_bias_pin": "VNB",
    "voltage_name": "VGND"
  },
  "pg_pin VNB": {
    "pg_type": "pwell",
    "voltage_name": "VNB"
  },
  "pg_pin VPB": {
    "pg_type": "nwell",
    "voltage_name": "VPB"
  },
  "pg_pin VPWR": {
    "pg_type": "primary_power",
    "related_bias_pin": "VPB",
    "voltage_name": "VPWR"
  },
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    "clock": "false",
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      "rise_power power_inputs_1": {
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    "max_transition": 1.5,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.002418
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  "pin B": {
    "capacitance": 0.002213,
    "clock": "false",
    "direction": "input",
    "fall_capacitance": 0.002061,
    "internal_power": {
      "fall_power power_inputs_1": {
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        "values": [
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      "rise_power power_inputs_1": {
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        "values": [
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    },
    "max_transition": 1.5,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.002365
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  "pin C_N": {
    "capacitance": 0.001468,
    "clock": "false",
    "direction": "input",
    "fall_capacitance": 0.001374,
    "internal_power": {
      "fall_power power_inputs_1": {
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      "rise_power power_inputs_1": {
        "index_1": [
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          0.650743,
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        "values": [
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          0.0015759,
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    },
    "max_transition": 1.5,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.001562
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  "pin X": {
    "direction": "output",
    "function": "(A) | (B) | (!C_N)",
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        "related_pin": "A",
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        "when": "(!B&C_N)"
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      {
        "fall_power power_outputs_1": {
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        "related_pin": "B",
        "rise_power power_outputs_1": {
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        "when": "(!A&C_N)"
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      {
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    "max_capacitance": 0.271922,
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    "power_down_function": "(!VPWR + VGND)",
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "timing": [
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