{
  "area": 20.0192,
  "cell_footprint": "dlxtn",
  "cell_leakage_power": 0.0,
  "latch IQ,IQ_N": {
    "data_in": "D",
    "enable": "!GATE_N"
  },
  "pg_pin VGND": {
    "pg_type": "primary_ground",
    "related_bias_pin": "VNB",
    "voltage_name": "VGND"
  },
  "pg_pin VNB": {
    "pg_type": "pwell",
    "voltage_name": "VNB"
  },
  "pg_pin VPB": {
    "pg_type": "nwell",
    "voltage_name": "VPB"
  },
  "pg_pin VPWR": {
    "pg_type": "primary_power",
    "related_bias_pin": "VPB",
    "voltage_name": "VPWR"
  },
  "pin D": {
    "capacitance": 0.001726,
    "clock": "false",
    "direction": "input",
    "fall_capacitance": 0.00162,
    "internal_power": {
      "fall_power power_inputs_1": {
        "index_1": [
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          0.0230506,
          0.0531329,
          0.122474,
          0.282311,
          0.650743,
          1.5
        ],
        "values": [
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          0.0057927,
          0.0057635,
          0.005696,
          0.0055406
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      },
      "rise_power power_inputs_1": {
        "index_1": [
          0.01,
          0.0230506,
          0.0531329,
          0.122474,
          0.282311,
          0.650743,
          1.5
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        "values": [
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          0.0017552,
          0.0016917,
          0.0015453,
          0.0012077
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      }
    },
    "max_transition": 1.5,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.001833,
    "timing": [
      {
        "fall_constraint vio_3_3_1": {
          "index_1": [
            0.01,
            0.5,
            1.5
          ],
          "index_2": [
            0.01,
            0.5,
            1.5
          ],
          "values": [
            [
              0.146043,
              0.3195293,
              0.5746563
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            [
              0.0885234,
              0.2632305,
              0.5195781
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            [
              0.0897441,
              0.2583477,
              0.5110332
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          ]
        },
        "related_pin": "GATE_N",
        "rise_constraint vio_3_3_1": {
          "index_1": [
            0.01,
            0.5,
            1.5
          ],
          "index_2": [
            0.01,
            0.5,
            1.5
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          "values": [
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              0.3036602,
              0.3561504
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            [
              0.1141582,
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              0.2498027
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            [
              0.0213848,
              0.1045391,
              0.1594707
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          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_rising",
        "violation_delay_degrade_pct": 10.0
      },
      {
        "fall_constraint vio_3_3_1": {
          "index_1": [
            0.01,
            0.5,
            1.5
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          "index_2": [
            0.01,
            0.5,
            1.5
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          "values": [
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              -0.1176289,
              -0.2972188,
              -0.5572285
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            [
              -0.0674336,
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              -0.5033711
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            [
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              -0.232375,
              -0.4899434
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        },
        "related_pin": "GATE_N",
        "rise_constraint vio_3_3_1": {
          "index_1": [
            0.01,
            0.5,
            1.5
          ],
          "index_2": [
            0.01,
            0.5,
            1.5
          ],
          "values": [
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              -0.1969746,
              -0.2825703,
              -0.3362812
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            [
              -0.090627,
              -0.1750019,
              -0.2287129
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            [
              0.0009258,
              -0.0846699,
              -0.1408223
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          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10.0
      }
    ]
  },
  "pin GATE_N": {
    "capacitance": 0.001577,
    "clock": "true",
    "direction": "input",
    "fall_capacitance": 0.00155,
    "internal_power": {
      "fall_power power_inputs_1": {
        "index_1": [
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          0.0230506,
          0.0531329,
          0.122474,
          0.282311,
          0.650743,
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        "values": [
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          0.0128069,
          0.0127554,
          0.0126368
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      },
      "rise_power power_inputs_1": {
        "index_1": [
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          0.0230506,
          0.0531329,
          0.122474,
          0.282311,
          0.650743,
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        "values": [
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          0.0075956,
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          0.00748,
          0.0072942,
          0.0068659
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      }
    },
    "max_transition": 1.5,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.001764,
    "timing": {
      "fall_constraint constraint_3_0_1": {
        "index_1": [
          0.01,
          0.5,
          1.5
        ],
        "values": [
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          0.627,
          1.877
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      },
      "related_pin": "GATE_N",
      "sim_opt": "runlvl=5 accurate=1",
      "timing_type": "min_pulse_width",
      "violation_delay_degrade_pct": 10.0
    }
  },
  "pin Q": {
    "direction": "output",
    "function": "IQ",
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      {
        "fall_power scalar": {
          "values": [
            0.0
          ]
        },
        "related_pin": "GATE_N",
        "rise_power power_outputs_1": {
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            [
              0.0260316,
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            [
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              0.0306209,
              0.0410986,
              0.0707257,
              0.1560021,
              0.404532
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          ]
        },
        "when": "(D)"
      },
      {
        "fall_power power_outputs_1": {
          "index_1": [
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            0.0531329,
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            0.650743,
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          "index_2": [
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          "values": [
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        },
        "related_pin": "GATE_N",
        "rise_power scalar": {
          "values": [
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          ]
        },
        "when": "(!D)"
      },
      {
        "fall_power power_outputs_1": {
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              -0.3542193
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          ]
        },
        "related_pin": "D",
        "rise_power power_outputs_1": {
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          "values": [
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          ]
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        "when": "(!GATE_N)"
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    ],
    "max_capacitance": 0.31518,
    "max_transition": 1.503893,
    "power_down_function": "(!VPWR + VGND)",
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "timing": [
      {
        "cell_fall del_1_7_7": {
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        "cell_rise del_1_7_7": {
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        "fall_transition del_1_7_7": {
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        "rise_transition del_1_7_7": {
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        },
        "sdf_cond": "GATEN==1'b0",
        "timing_sense": "positive_unate",
        "timing_type": "combinational",
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      },
      {
        "cell_rise del_1_7_7": {
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