models/udp_pwrgood_pp_p/definition.json

{
 "description": "UDP_OUT :=x when VPWR!=1\nUDP_OUT :=UDP_IN when VPWR==1",
 "file_prefix": "sky130_fd_sc_hdll__udp_pwrgood_pp_p",
 "library": "sky130_fd_sc_hdll",
 "name": "udp_pwrgood_pp$P",
 "parameters": [],
 "ports": [
  [
   "signal",
   "UDP_OUT",
   "output",
   ""
  ],
  [
   "signal",
   "UDP_IN",
   "input",
   ""
  ],
  [
   "power",
   "VPWR",
   "input",
   "supply1"
  ]
 ],
 "type": "primitive",
 "verilog_name": "sky130_fd_sc_hdll__udp_pwrgood_pp$P"
}