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foss-eda-tools / skywater-pdk / libs / sky130_fd_sc_hdll / refs/heads/branch-0.1.0 / . / cells / sedfxbp / sky130_fd_sc_hdll__sedfxbp_1__ss_100C_1v60.lib.json
blob: f3fd75ac42eae8ae3c50db8330446dc93bdd0f67 [file] [log] [blame]
{
"area": 41.2896,
"cell_footprint": "sky130_fd_sc_hdll__sedfxbp",
"cell_leakage_power": 9.421105,
"ff,IQ,IQ_N": {
"clocked_on": "CLK",
"next_state": "(D&DE&!SCE) | (IQ&!DE&!SCE) | (SCD&SCE)"
},
"leakage_power": [
{
"value": 9.91517,
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},
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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},
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0.282311,
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1.5
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]
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}
]
},
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}
},
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"nextstate_type": "scan_in",
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"related_power_pin": "VPWR",
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"index_2": [
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"values": [
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},
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0.01,
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0.1654277,
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0.0360332,
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},
"sim_opt": "runlvl=5 accurate=1",
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"violation_delay_degrade_pct": 10.0
},
{
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"index_2": [
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},
"related_pin": "CLK",
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"index_2": [
0.01,
0.5,
1.5
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"values": [
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[
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]
},
"sim_opt": "runlvl=5 accurate=1",
"timing_type": "hold_rising",
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}
]
},
"pin,SCE": {
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"clock": "false",
"direction": "input",
"fall_capacitance": 0.002922,
"internal_power": {
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0.01,
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0.122474,
0.282311,
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1.5
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"values": [
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0.009095,
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},
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"values": [
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0.0068012,
0.0069139,
0.0071737,
0.0077726
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}
},
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"nextstate_type": "scan_enable",
"related_ground_pin": "VGND",
"related_power_pin": "VPWR",
"rise_capacitance": 0.003,
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{
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"index_1": [
0.01,
0.5,
1.5
],
"index_2": [
0.01,
0.5,
1.5
],
"values": [
[
0.7515117,
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[
0.5645976,
0.7148906,
1.0188457
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[
0.2887188,
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0.7478496
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]
},
"related_pin": "CLK",
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"index_1": [
0.01,
0.5,
1.5
],
"index_2": [
0.01,
0.5,
1.5
],
"values": [
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0.7417461,
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1.0788066
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[
0.5511699,
0.7039043,
0.8906719
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[
0.2838359,
0.4365703,
0.6196758
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]
},
"sim_opt": "runlvl=5 accurate=1",
"timing_type": "setup_rising",
"violation_delay_degrade_pct": 10.0
},
{
"fall_constraint,vio_3_3_1": {
"index_1": [
0.01,
0.5,
1.5
],
"index_2": [
0.01,
0.5,
1.5
],
"values": [
[
-0.3971699,
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],
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[
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]
},
"related_pin": "CLK",
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"index_1": [
0.01,
0.5,
1.5
],
"index_2": [
0.01,
0.5,
1.5
],
"values": [
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[
0.0216777,
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]
},
"sim_opt": "runlvl=5 accurate=1",
"timing_type": "hold_rising",
"violation_delay_degrade_pct": 10.0
}
]
},
"test_cell": {
"ff,IQ,IQ_N": {
"clocked_on": "CLK",
"next_state": "(D&DE) | (IQ&!DE)"
},
"pin,CLK": {
"direction": "input"
},
"pin,D": {
"direction": "input"
},
"pin,DE": {
"direction": "input"
},
"pin,Q": {
"direction": "output",
"function": "IQ",
"signal_type": "test_scan_out"
},
"pin,Q_N": {
"direction": "output",
"function": "IQ_N",
"signal_type": "test_scan_out_inverted"
},
"pin,SCD": {
"direction": "input",
"signal_type": "test_scan_in"
},
"pin,SCE": {
"direction": "input",
"signal_type": "test_scan_enable"
}
}
}