)]}'
{
  "commit": "dba9671a44909083f9a5eabed74d20e5e6d7f5f5",
  "tree": "0d83225a6c5966045291f80b42ad4cb4574cd5b3",
  "parents": [
    "e0538afe79677fc0d5e8e5d76016ad50e9088ddc"
  ],
  "author": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "me@mith.ro",
    "time": "Fri Oct 02 10:01:02 2020 -0700"
  },
  "committer": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "tansell@google.com",
    "time": "Fri Oct 02 10:01:02 2020 -0700"
  },
  "message": "verilog: Fixing include path.\n\nThe include lines previously had,\n`include \"sky130_fd_sc_hd__o221a.pp.functional.v\"`\nbut the actual filename is\n`include \"sky130_fd_sc_hd__o221a.functional.pp.v\"`.\n\nSigned-off-by: Tim \u0027mithro\u0027 Ansell \u003ctansell@google.com\u003e\n",
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