| { |
| "area": 21.2704, |
| "cell_footprint": "sky130_fd_sc_hdll__sdlclkp", |
| "cell_leakage_power": 0.003645634, |
| "clock_gating_integrated_cell": "latch_posedge_precontrol", |
| "leakage_power": [ |
| { |
| "value": 0.0047133, |
| "when": "CLK&!GATE&!GCLK&!SCE" |
| }, |
| { |
| "value": 0.002881, |
| "when": "!CLK&GATE&!GCLK&!SCE" |
| }, |
| { |
| "value": 0.0029311, |
| "when": "!CLK&!GATE&!GCLK&SCE" |
| }, |
| { |
| "value": 0.0030049, |
| "when": "CLK&!GATE&GCLK&SCE" |
| }, |
| { |
| "value": 0.0026546, |
| "when": "!CLK&GATE&!GCLK&SCE" |
| }, |
| { |
| "value": 0.0039222, |
| "when": "!CLK&!GATE&!GCLK&!SCE" |
| }, |
| { |
| "value": 0.0029528, |
| "when": "CLK&GATE&GCLK&!SCE" |
| }, |
| { |
| "value": 0.0027274, |
| "when": "CLK&GATE&GCLK&SCE" |
| }, |
| { |
| "value": 0.0046521, |
| "when": "CLK&GATE&!GCLK&!SCE" |
| }, |
| { |
| "value": 0.0047043, |
| "when": "CLK&!GATE&!GCLK&SCE" |
| }, |
| { |
| "value": 0.0044352, |
| "when": "CLK&GATE&!GCLK&SCE" |
| }, |
| { |
| "value": 0.0041686, |
| "when": "CLK&!GATE&GCLK&!SCE" |
| } |
| ], |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
| "pg_type": "primary_power", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
| "capacitance": 0.003664, |
| "clock": "true", |
| "clock_gate_clock_pin": "true", |
| "direction": "input", |
| "fall_capacitance": 0.003482, |
| "internal_power": { |
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| 0.01, |
| 0.0230506, |
| 0.0531329, |
| 0.122474, |
| 0.282311, |
| 0.650743, |
| 1.5 |
| ], |
| "values": [ |
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| 0.0194071, |
| 0.0192731, |
| 0.0193227, |
| 0.0194369, |
| 0.0197001, |
| 0.0203068 |
| ] |
| }, |
| "rise_power,power_inputs_1": { |
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| 0.01, |
| 0.0230506, |
| 0.0531329, |
| 0.122474, |
| 0.282311, |
| 0.650743, |
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| 0.0086674, |
| 0.008577, |
| 0.0085548, |
| 0.0085036, |
| 0.0083858, |
| 0.008114 |
| ] |
| } |
| }, |
| "max_transition": 1.5, |
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| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.003894, |
| "timing": { |
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| "index_1": [ |
| 0.01, |
| 0.5, |
| 1.5 |
| ], |
| "values": [ |
| 0.2248516, |
| 0.627, |
| 1.877 |
| ] |
| }, |
| "related_pin": "CLK", |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "min_pulse_width", |
| "violation_delay_degrade_pct": 10.0 |
| } |
| }, |
| "pin,GATE": { |
| "capacitance": 0.001945, |
| "clock": "false", |
| "clock_gate_enable_pin": "true", |
| "direction": "input", |
| "fall_capacitance": 0.001768, |
| "internal_power": { |
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| 0.01, |
| 0.0230506, |
| 0.0531329, |
| 0.122474, |
| 0.282311, |
| 0.650743, |
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| 0.0240377, |
| 0.0241253, |
| 0.0243272, |
| 0.0247926, |
| 0.0258653 |
| ] |
| }, |
| "rise_power,power_inputs_1": { |
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| 0.01, |
| 0.0230506, |
| 0.0531329, |
| 0.122474, |
| 0.282311, |
| 0.650743, |
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| 0.0152361, |
| 0.0151257, |
| 0.0151055, |
| 0.0150588, |
| 0.0149512, |
| 0.0147033 |
| ] |
| } |
| }, |
| "max_transition": 1.5, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.002122, |
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| { |
| "fall_constraint,vio_3_3_1": { |
| "index_1": [ |
| 0.01, |
| 0.5, |
| 1.5 |
| ], |
| "index_2": [ |
| 0.01, |
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| 1.5 |
| ], |
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| [ |
| 0.2021953, |
| 0.353709, |
| 0.6283672 |
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| [ |
| 0.1202617, |
| 0.2729961, |
| 0.5452129 |
| ], |
| [ |
| 0.0653301, |
| 0.2168438, |
| 0.4866191 |
| ] |
| ] |
| }, |
| "related_pin": "CLK", |
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| 0.01, |
| 0.5, |
| 1.5 |
| ], |
| "index_2": [ |
| 0.01, |
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| [ |
| 0.0555645, |
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| [ |
| 0.0750957, |
| 0.170457, |
| 0.2449199 |
| ] |
| ] |
| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "setup_rising", |
| "violation_delay_degrade_pct": 10.0 |
| }, |
| { |
| "fall_constraint,vio_3_3_1": { |
| "index_1": [ |
| 0.01, |
| 0.5, |
| 1.5 |
| ], |
| "index_2": [ |
| 0.01, |
| 0.5, |
| 1.5 |
| ], |
| "values": [ |
| [ |
| -0.1811055, |
| -0.3313985, |
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| [ |
| -0.1113789, |
| -0.2641133, |
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| [ |
| -0.0588887, |
| -0.2091816, |
| -0.4765156 |
| ] |
| ] |
| }, |
| "related_pin": "CLK", |
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| 0.01, |
| 0.5, |
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| -0.0529316, |
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| [ |
| -0.0088398, |
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| [ |
| -0.0002949, |
| -0.0919941, |
| -0.1579121 |
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| ] |
| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "hold_rising", |
| "violation_delay_degrade_pct": 10.0 |
| } |
| ] |
| }, |
| "pin,GCLK": { |
| "clock_gate_out_pin": "true", |
| "direction": "output", |
| "internal_power": [ |
| { |
| "fall_power,power_outputs_1": { |
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| 0.01, |
| 0.0230506, |
| 0.0531329, |
| 0.122474, |
| 0.282311, |
| 0.650743, |
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| 0.0005, |
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| 0.01009812, |
| 0.02749987, |
| 0.07488948, |
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| 0.0130161, |
| 0.0117533, |
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| [ |
| 0.0128811, |
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| [ |
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| [ |
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| "related_pin": "CLK", |
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| "when": "(!GATE&SCE)" |
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| { |
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| "related_pin": "CLK", |
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| "when": "(GATE&!SCE)" |
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| { |
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| { |
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| ] |
| }, |
| "statetable,CLK GATE SCE,M0": { |
| "table": [ |
| "L L L : - : L", |
| "L L H : - : H", |
| "L H L : - : H", |
| "L H H : - : H", |
| "H - - : - : N" |
| ] |
| } |
| } |
