| { | |
| "area": 8.7584, | |
| "cell_footprint": "sky130_fd_sc_hdll__a32oi", | |
| "cell_leakage_power": 1.176846, | |
| "leakage_power": [ | |
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| "value": 0.981495, | |
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| { | |
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| }, | |
| { | |
| "value": 0.124718, | |
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| }, | |
| { | |
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| }, | |
| { | |
| "value": 0.668083, | |
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| }, | |
| { | |
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| }, | |
| { | |
| "value": 0.11302, | |
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| }, | |
| { | |
| "value": 1.78128, | |
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| }, | |
| { | |
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| }, | |
| { | |
| "value": 1.95504, | |
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| { | |
| "value": 1.05942, | |
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| }, | |
| { | |
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| { | |
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| }, | |
| { | |
| "value": 1.00696, | |
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| }, | |
| { | |
| "value": 0.11133, | |
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| }, | |
| { | |
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| }, | |
| { | |
| "value": 0.654696, | |
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| }, | |
| { | |
| "value": 1.70986, | |
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| }, | |
| { | |
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| { | |
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| { | |
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| { | |
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| { | |
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| { | |
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| { | |
| "value": 1.17254, | |
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| { | |
| "value": 1.91287, | |
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| }, | |
| { | |
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| { | |
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| }, | |
| { | |
| "value": 1.94476, | |
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| "pg_type": "primary_ground", | |
| "related_bias_pin": "VPB", | |
| "voltage_name": "VGND" | |
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| "pg_pin,VNB": { | |
| "pg_type": "nwell", | |
| "physical_connection": "device_layer", | |
| "voltage_name": "VNB" | |
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| "pg_pin,VPB": { | |
| "pg_type": "pwell", | |
| "physical_connection": "device_layer", | |
| "voltage_name": "VPB" | |
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| "related_bias_pin": "VNB", | |
| "voltage_name": "VPWR" | |
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| "clock": "false", | |
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| 0.0039647 | |
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| "related_power_pin": "VPWR", | |
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| "pin,A2": { | |
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| "related_power_pin": "VPWR", | |
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| }, | |
| "pin,A3": { | |
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| "pin,B1": { | |
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| }, | |
| "pin,B2": { | |
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| "clock": "false", | |
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| "fall_capacitance": 0.002167, | |
| "internal_power": { | |
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| }, | |
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| "related_ground_pin": "VGND", | |
| "related_power_pin": "VPWR", | |
| "rise_capacitance": 0.002534 | |
| }, | |
| "pin,Y": { | |
| "direction": "output", | |
| "function": "(!A1&!B1) | (!A1&!B2) | (!A2&!B1) | (!A3&!B1) | (!A2&!B2) | (!A3&!B2)", | |
| "internal_power": [ | |
| { | |
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| [ | |
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| [ | |
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| [ | |
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| [ | |
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| }, | |
| "related_pin": "A1", | |
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| [ | |
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| [ | |
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| [ | |
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| [ | |
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| ] | |
| }, | |
| "when": "(A2&A3&!B1&!B2)" | |
| }, | |
| { | |
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| }, | |
| "related_pin": "A1", | |
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