)]}'
{
  "commit": "90c66351742f53b63d4508edf728c41a5b4a1bc8",
  "tree": "fbd166177719e33a2867bba13e05869040db6dfb",
  "parents": [
    "17864216b91d1af4efdfc443ff274032212a7012",
    "4ccac0c76bfd167ff96a70e24162775d05fd131d"
  ],
  "author": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "me@mith.ro",
    "time": "Wed Oct 28 20:04:38 2020 -0700"
  },
  "committer": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "tansell@google.com",
    "time": "Wed Oct 28 20:04:38 2020 -0700"
  },
  "message": "verilog: Fixing power pins usage in non-powerpin mode.\n\nPreviously even when `USE_POWER_PIN` was not defined, the drive strength\nwrappers where still defining the power pins as ports.\n\nFixes https://github.com/google/skywater-pdk/issues/181\n\nSigned-off-by: Tim \u0027mithro\u0027 Ansell \u003ctansell@google.com\u003e\n",
  "tree_diff": []
}