verilog: Fixing power pins usage in non-powerpin mode.
Previously even when `USE_POWER_PIN` was not defined, the drive strength
wrappers where still defining the power pins as ports.
Fixes https://github.com/google/skywater-pdk/issues/181
Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>
diff --git a/cells/a211o/sky130_fd_sc_hdll__a211o_1.v b/cells/a211o/sky130_fd_sc_hdll__a211o_1.v
index 00cc9b2..b74e365 100644
--- a/cells/a211o/sky130_fd_sc_hdll__a211o_1.v
+++ b/cells/a211o/sky130_fd_sc_hdll__a211o_1.v
@@ -80,26 +80,18 @@
`celldefine
module sky130_fd_sc_hdll__a211o_1 (
- X ,
- A1 ,
- A2 ,
- B1 ,
- C1 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A1,
+ A2,
+ B1,
+ C1
);
- output X ;
- input A1 ;
- input A2 ;
- input B1 ;
- input C1 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input C1;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/a211o/sky130_fd_sc_hdll__a211o_2.v b/cells/a211o/sky130_fd_sc_hdll__a211o_2.v
index 7ce49ff..972f000 100644
--- a/cells/a211o/sky130_fd_sc_hdll__a211o_2.v
+++ b/cells/a211o/sky130_fd_sc_hdll__a211o_2.v
@@ -80,26 +80,18 @@
`celldefine
module sky130_fd_sc_hdll__a211o_2 (
- X ,
- A1 ,
- A2 ,
- B1 ,
- C1 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A1,
+ A2,
+ B1,
+ C1
);
- output X ;
- input A1 ;
- input A2 ;
- input B1 ;
- input C1 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input C1;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/a211o/sky130_fd_sc_hdll__a211o_4.v b/cells/a211o/sky130_fd_sc_hdll__a211o_4.v
index cf28ea9..e1c06e4 100644
--- a/cells/a211o/sky130_fd_sc_hdll__a211o_4.v
+++ b/cells/a211o/sky130_fd_sc_hdll__a211o_4.v
@@ -80,26 +80,18 @@
`celldefine
module sky130_fd_sc_hdll__a211o_4 (
- X ,
- A1 ,
- A2 ,
- B1 ,
- C1 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A1,
+ A2,
+ B1,
+ C1
);
- output X ;
- input A1 ;
- input A2 ;
- input B1 ;
- input C1 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input C1;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/a211oi/sky130_fd_sc_hdll__a211oi_1.v b/cells/a211oi/sky130_fd_sc_hdll__a211oi_1.v
index ee92194..f554993 100644
--- a/cells/a211oi/sky130_fd_sc_hdll__a211oi_1.v
+++ b/cells/a211oi/sky130_fd_sc_hdll__a211oi_1.v
@@ -80,26 +80,18 @@
`celldefine
module sky130_fd_sc_hdll__a211oi_1 (
- Y ,
- A1 ,
- A2 ,
- B1 ,
- C1 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A1,
+ A2,
+ B1,
+ C1
);
- output Y ;
- input A1 ;
- input A2 ;
- input B1 ;
- input C1 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input C1;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/a211oi/sky130_fd_sc_hdll__a211oi_2.v b/cells/a211oi/sky130_fd_sc_hdll__a211oi_2.v
index 11e1652..b807441 100644
--- a/cells/a211oi/sky130_fd_sc_hdll__a211oi_2.v
+++ b/cells/a211oi/sky130_fd_sc_hdll__a211oi_2.v
@@ -80,26 +80,18 @@
`celldefine
module sky130_fd_sc_hdll__a211oi_2 (
- Y ,
- A1 ,
- A2 ,
- B1 ,
- C1 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A1,
+ A2,
+ B1,
+ C1
);
- output Y ;
- input A1 ;
- input A2 ;
- input B1 ;
- input C1 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input C1;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/a211oi/sky130_fd_sc_hdll__a211oi_4.v b/cells/a211oi/sky130_fd_sc_hdll__a211oi_4.v
index 8f9f4ab..b95d860 100644
--- a/cells/a211oi/sky130_fd_sc_hdll__a211oi_4.v
+++ b/cells/a211oi/sky130_fd_sc_hdll__a211oi_4.v
@@ -80,26 +80,18 @@
`celldefine
module sky130_fd_sc_hdll__a211oi_4 (
- Y ,
- A1 ,
- A2 ,
- B1 ,
- C1 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A1,
+ A2,
+ B1,
+ C1
);
- output Y ;
- input A1 ;
- input A2 ;
- input B1 ;
- input C1 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input C1;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/a21bo/sky130_fd_sc_hdll__a21bo_1.v b/cells/a21bo/sky130_fd_sc_hdll__a21bo_1.v
index ce3f22e..3427e9d 100644
--- a/cells/a21bo/sky130_fd_sc_hdll__a21bo_1.v
+++ b/cells/a21bo/sky130_fd_sc_hdll__a21bo_1.v
@@ -81,21 +81,13 @@
X ,
A1 ,
A2 ,
- B1_N,
- VPWR,
- VGND,
- VPB ,
- VNB
+ B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/a21bo/sky130_fd_sc_hdll__a21bo_2.v b/cells/a21bo/sky130_fd_sc_hdll__a21bo_2.v
index 9b3754a..35b8cad 100644
--- a/cells/a21bo/sky130_fd_sc_hdll__a21bo_2.v
+++ b/cells/a21bo/sky130_fd_sc_hdll__a21bo_2.v
@@ -81,21 +81,13 @@
X ,
A1 ,
A2 ,
- B1_N,
- VPWR,
- VGND,
- VPB ,
- VNB
+ B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/a21bo/sky130_fd_sc_hdll__a21bo_4.v b/cells/a21bo/sky130_fd_sc_hdll__a21bo_4.v
index e8e13ce..f486d0e 100644
--- a/cells/a21bo/sky130_fd_sc_hdll__a21bo_4.v
+++ b/cells/a21bo/sky130_fd_sc_hdll__a21bo_4.v
@@ -81,21 +81,13 @@
X ,
A1 ,
A2 ,
- B1_N,
- VPWR,
- VGND,
- VPB ,
- VNB
+ B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/a21boi/sky130_fd_sc_hdll__a21boi_1.v b/cells/a21boi/sky130_fd_sc_hdll__a21boi_1.v
index 0716fdb..1b5724e 100644
--- a/cells/a21boi/sky130_fd_sc_hdll__a21boi_1.v
+++ b/cells/a21boi/sky130_fd_sc_hdll__a21boi_1.v
@@ -81,21 +81,13 @@
Y ,
A1 ,
A2 ,
- B1_N,
- VPWR,
- VGND,
- VPB ,
- VNB
+ B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/a21boi/sky130_fd_sc_hdll__a21boi_2.v b/cells/a21boi/sky130_fd_sc_hdll__a21boi_2.v
index bb8e67a..6ffe7f5 100644
--- a/cells/a21boi/sky130_fd_sc_hdll__a21boi_2.v
+++ b/cells/a21boi/sky130_fd_sc_hdll__a21boi_2.v
@@ -81,21 +81,13 @@
Y ,
A1 ,
A2 ,
- B1_N,
- VPWR,
- VGND,
- VPB ,
- VNB
+ B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/a21boi/sky130_fd_sc_hdll__a21boi_4.v b/cells/a21boi/sky130_fd_sc_hdll__a21boi_4.v
index 137eb78..7243a35 100644
--- a/cells/a21boi/sky130_fd_sc_hdll__a21boi_4.v
+++ b/cells/a21boi/sky130_fd_sc_hdll__a21boi_4.v
@@ -81,21 +81,13 @@
Y ,
A1 ,
A2 ,
- B1_N,
- VPWR,
- VGND,
- VPB ,
- VNB
+ B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_1.v b/cells/a21o/sky130_fd_sc_hdll__a21o_1.v
index fb48b5d..fe258c4 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_1.v
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_1.v
@@ -77,24 +77,16 @@
`celldefine
module sky130_fd_sc_hdll__a21o_1 (
- X ,
- A1 ,
- A2 ,
- B1 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A1,
+ A2,
+ B1
);
- output X ;
- input A1 ;
- input A2 ;
- input B1 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A1;
+ input A2;
+ input B1;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_2.v b/cells/a21o/sky130_fd_sc_hdll__a21o_2.v
index 03fff8f..e575745 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_2.v
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_2.v
@@ -77,24 +77,16 @@
`celldefine
module sky130_fd_sc_hdll__a21o_2 (
- X ,
- A1 ,
- A2 ,
- B1 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A1,
+ A2,
+ B1
);
- output X ;
- input A1 ;
- input A2 ;
- input B1 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A1;
+ input A2;
+ input B1;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_4.v b/cells/a21o/sky130_fd_sc_hdll__a21o_4.v
index 248abe0..7126fc9 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_4.v
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_4.v
@@ -77,24 +77,16 @@
`celldefine
module sky130_fd_sc_hdll__a21o_4 (
- X ,
- A1 ,
- A2 ,
- B1 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A1,
+ A2,
+ B1
);
- output X ;
- input A1 ;
- input A2 ;
- input B1 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A1;
+ input A2;
+ input B1;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_6.v b/cells/a21o/sky130_fd_sc_hdll__a21o_6.v
index aeff63b..3f5dd81 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_6.v
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_6.v
@@ -77,24 +77,16 @@
`celldefine
module sky130_fd_sc_hdll__a21o_6 (
- X ,
- A1 ,
- A2 ,
- B1 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A1,
+ A2,
+ B1
);
- output X ;
- input A1 ;
- input A2 ;
- input B1 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A1;
+ input A2;
+ input B1;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_8.v b/cells/a21o/sky130_fd_sc_hdll__a21o_8.v
index a78f276..3ec8613 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_8.v
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_8.v
@@ -77,24 +77,16 @@
`celldefine
module sky130_fd_sc_hdll__a21o_8 (
- X ,
- A1 ,
- A2 ,
- B1 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A1,
+ A2,
+ B1
);
- output X ;
- input A1 ;
- input A2 ;
- input B1 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A1;
+ input A2;
+ input B1;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/a21oi/sky130_fd_sc_hdll__a21oi_1.v b/cells/a21oi/sky130_fd_sc_hdll__a21oi_1.v
index 9c37f93..1cc8d19 100644
--- a/cells/a21oi/sky130_fd_sc_hdll__a21oi_1.v
+++ b/cells/a21oi/sky130_fd_sc_hdll__a21oi_1.v
@@ -77,24 +77,16 @@
`celldefine
module sky130_fd_sc_hdll__a21oi_1 (
- Y ,
- A1 ,
- A2 ,
- B1 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A1,
+ A2,
+ B1
);
- output Y ;
- input A1 ;
- input A2 ;
- input B1 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/a21oi/sky130_fd_sc_hdll__a21oi_2.v b/cells/a21oi/sky130_fd_sc_hdll__a21oi_2.v
index 0b352ad..0bbb7c8 100644
--- a/cells/a21oi/sky130_fd_sc_hdll__a21oi_2.v
+++ b/cells/a21oi/sky130_fd_sc_hdll__a21oi_2.v
@@ -77,24 +77,16 @@
`celldefine
module sky130_fd_sc_hdll__a21oi_2 (
- Y ,
- A1 ,
- A2 ,
- B1 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A1,
+ A2,
+ B1
);
- output Y ;
- input A1 ;
- input A2 ;
- input B1 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/a21oi/sky130_fd_sc_hdll__a21oi_4.v b/cells/a21oi/sky130_fd_sc_hdll__a21oi_4.v
index 11f89cc..95a4b7a 100644
--- a/cells/a21oi/sky130_fd_sc_hdll__a21oi_4.v
+++ b/cells/a21oi/sky130_fd_sc_hdll__a21oi_4.v
@@ -77,24 +77,16 @@
`celldefine
module sky130_fd_sc_hdll__a21oi_4 (
- Y ,
- A1 ,
- A2 ,
- B1 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A1,
+ A2,
+ B1
);
- output Y ;
- input A1 ;
- input A2 ;
- input B1 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/a221oi/sky130_fd_sc_hdll__a221oi_1.v b/cells/a221oi/sky130_fd_sc_hdll__a221oi_1.v
index b577243..ded1c30 100644
--- a/cells/a221oi/sky130_fd_sc_hdll__a221oi_1.v
+++ b/cells/a221oi/sky130_fd_sc_hdll__a221oi_1.v
@@ -83,28 +83,20 @@
`celldefine
module sky130_fd_sc_hdll__a221oi_1 (
- Y ,
- A1 ,
- A2 ,
- B1 ,
- B2 ,
- C1 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A1,
+ A2,
+ B1,
+ B2,
+ C1
);
- output Y ;
- input A1 ;
- input A2 ;
- input B1 ;
- input B2 ;
- input C1 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
+ input C1;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/a221oi/sky130_fd_sc_hdll__a221oi_2.v b/cells/a221oi/sky130_fd_sc_hdll__a221oi_2.v
index 5eda31e..dbad1c7 100644
--- a/cells/a221oi/sky130_fd_sc_hdll__a221oi_2.v
+++ b/cells/a221oi/sky130_fd_sc_hdll__a221oi_2.v
@@ -83,28 +83,20 @@
`celldefine
module sky130_fd_sc_hdll__a221oi_2 (
- Y ,
- A1 ,
- A2 ,
- B1 ,
- B2 ,
- C1 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A1,
+ A2,
+ B1,
+ B2,
+ C1
);
- output Y ;
- input A1 ;
- input A2 ;
- input B1 ;
- input B2 ;
- input C1 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
+ input C1;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/a221oi/sky130_fd_sc_hdll__a221oi_4.v b/cells/a221oi/sky130_fd_sc_hdll__a221oi_4.v
index 2cc8059..8d11d27 100644
--- a/cells/a221oi/sky130_fd_sc_hdll__a221oi_4.v
+++ b/cells/a221oi/sky130_fd_sc_hdll__a221oi_4.v
@@ -83,28 +83,20 @@
`celldefine
module sky130_fd_sc_hdll__a221oi_4 (
- Y ,
- A1 ,
- A2 ,
- B1 ,
- B2 ,
- C1 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A1,
+ A2,
+ B1,
+ B2,
+ C1
);
- output Y ;
- input A1 ;
- input A2 ;
- input B1 ;
- input B2 ;
- input C1 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
+ input C1;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/a222oi/sky130_fd_sc_hdll__a222oi_1.v b/cells/a222oi/sky130_fd_sc_hdll__a222oi_1.v
index 618368d..68e62a2 100644
--- a/cells/a222oi/sky130_fd_sc_hdll__a222oi_1.v
+++ b/cells/a222oi/sky130_fd_sc_hdll__a222oi_1.v
@@ -86,30 +86,22 @@
`celldefine
module sky130_fd_sc_hdll__a222oi_1 (
- Y ,
- A1 ,
- A2 ,
- B1 ,
- B2 ,
- C1 ,
- C2 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A1,
+ A2,
+ B1,
+ B2,
+ C1,
+ C2
);
- output Y ;
- input A1 ;
- input A2 ;
- input B1 ;
- input B2 ;
- input C1 ;
- input C2 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
+ input C1;
+ input C2;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/a22o/sky130_fd_sc_hdll__a22o_1.v b/cells/a22o/sky130_fd_sc_hdll__a22o_1.v
index e273e46..ddbb561 100644
--- a/cells/a22o/sky130_fd_sc_hdll__a22o_1.v
+++ b/cells/a22o/sky130_fd_sc_hdll__a22o_1.v
@@ -80,26 +80,18 @@
`celldefine
module sky130_fd_sc_hdll__a22o_1 (
- X ,
- A1 ,
- A2 ,
- B1 ,
- B2 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A1,
+ A2,
+ B1,
+ B2
);
- output X ;
- input A1 ;
- input A2 ;
- input B1 ;
- input B2 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/a22o/sky130_fd_sc_hdll__a22o_2.v b/cells/a22o/sky130_fd_sc_hdll__a22o_2.v
index 616e777..699277e 100644
--- a/cells/a22o/sky130_fd_sc_hdll__a22o_2.v
+++ b/cells/a22o/sky130_fd_sc_hdll__a22o_2.v
@@ -80,26 +80,18 @@
`celldefine
module sky130_fd_sc_hdll__a22o_2 (
- X ,
- A1 ,
- A2 ,
- B1 ,
- B2 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A1,
+ A2,
+ B1,
+ B2
);
- output X ;
- input A1 ;
- input A2 ;
- input B1 ;
- input B2 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/a22o/sky130_fd_sc_hdll__a22o_4.v b/cells/a22o/sky130_fd_sc_hdll__a22o_4.v
index f98e076..a131b7b 100644
--- a/cells/a22o/sky130_fd_sc_hdll__a22o_4.v
+++ b/cells/a22o/sky130_fd_sc_hdll__a22o_4.v
@@ -80,26 +80,18 @@
`celldefine
module sky130_fd_sc_hdll__a22o_4 (
- X ,
- A1 ,
- A2 ,
- B1 ,
- B2 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A1,
+ A2,
+ B1,
+ B2
);
- output X ;
- input A1 ;
- input A2 ;
- input B1 ;
- input B2 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/a22oi/sky130_fd_sc_hdll__a22oi_1.v b/cells/a22oi/sky130_fd_sc_hdll__a22oi_1.v
index 845aa5b..cfa7ffb 100644
--- a/cells/a22oi/sky130_fd_sc_hdll__a22oi_1.v
+++ b/cells/a22oi/sky130_fd_sc_hdll__a22oi_1.v
@@ -80,26 +80,18 @@
`celldefine
module sky130_fd_sc_hdll__a22oi_1 (
- Y ,
- A1 ,
- A2 ,
- B1 ,
- B2 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A1,
+ A2,
+ B1,
+ B2
);
- output Y ;
- input A1 ;
- input A2 ;
- input B1 ;
- input B2 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/a22oi/sky130_fd_sc_hdll__a22oi_2.v b/cells/a22oi/sky130_fd_sc_hdll__a22oi_2.v
index e977319..d6b398a 100644
--- a/cells/a22oi/sky130_fd_sc_hdll__a22oi_2.v
+++ b/cells/a22oi/sky130_fd_sc_hdll__a22oi_2.v
@@ -80,26 +80,18 @@
`celldefine
module sky130_fd_sc_hdll__a22oi_2 (
- Y ,
- A1 ,
- A2 ,
- B1 ,
- B2 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A1,
+ A2,
+ B1,
+ B2
);
- output Y ;
- input A1 ;
- input A2 ;
- input B1 ;
- input B2 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/a22oi/sky130_fd_sc_hdll__a22oi_4.v b/cells/a22oi/sky130_fd_sc_hdll__a22oi_4.v
index b1c6c59..0ad49a3 100644
--- a/cells/a22oi/sky130_fd_sc_hdll__a22oi_4.v
+++ b/cells/a22oi/sky130_fd_sc_hdll__a22oi_4.v
@@ -80,26 +80,18 @@
`celldefine
module sky130_fd_sc_hdll__a22oi_4 (
- Y ,
- A1 ,
- A2 ,
- B1 ,
- B2 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A1,
+ A2,
+ B1,
+ B2
);
- output Y ;
- input A1 ;
- input A2 ;
- input B1 ;
- input B2 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_1.v b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_1.v
index 36683b1..2f766bc 100644
--- a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_1.v
+++ b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_1.v
@@ -85,11 +85,7 @@
A1_N,
A2_N,
B1 ,
- B2 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ B2
);
output X ;
@@ -97,10 +93,6 @@
input A2_N;
input B1 ;
input B2 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_2.v b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_2.v
index 20c3a66..b2d156d 100644
--- a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_2.v
+++ b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_2.v
@@ -85,11 +85,7 @@
A1_N,
A2_N,
B1 ,
- B2 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ B2
);
output X ;
@@ -97,10 +93,6 @@
input A2_N;
input B1 ;
input B2 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_4.v b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_4.v
index 566082a..a767f28 100644
--- a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_4.v
+++ b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_4.v
@@ -85,11 +85,7 @@
A1_N,
A2_N,
B1 ,
- B2 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ B2
);
output X ;
@@ -97,10 +93,6 @@
input A2_N;
input B1 ;
input B2 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_1.v b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_1.v
index 8e6e061..32bcfa3 100644
--- a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_1.v
+++ b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_1.v
@@ -85,11 +85,7 @@
A1_N,
A2_N,
B1 ,
- B2 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ B2
);
output Y ;
@@ -97,10 +93,6 @@
input A2_N;
input B1 ;
input B2 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_2.v b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_2.v
index 46a1671..90fde46 100644
--- a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_2.v
+++ b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_2.v
@@ -85,11 +85,7 @@
A1_N,
A2_N,
B1 ,
- B2 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ B2
);
output Y ;
@@ -97,10 +93,6 @@
input A2_N;
input B1 ;
input B2 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_4.v b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_4.v
index 9e7cc5d..d5fee78 100644
--- a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_4.v
+++ b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_4.v
@@ -85,11 +85,7 @@
A1_N,
A2_N,
B1 ,
- B2 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ B2
);
output Y ;
@@ -97,10 +93,6 @@
input A2_N;
input B1 ;
input B2 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/a31o/sky130_fd_sc_hdll__a31o_1.v b/cells/a31o/sky130_fd_sc_hdll__a31o_1.v
index c506b61..141eaea 100644
--- a/cells/a31o/sky130_fd_sc_hdll__a31o_1.v
+++ b/cells/a31o/sky130_fd_sc_hdll__a31o_1.v
@@ -80,26 +80,18 @@
`celldefine
module sky130_fd_sc_hdll__a31o_1 (
- X ,
- A1 ,
- A2 ,
- A3 ,
- B1 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A1,
+ A2,
+ A3,
+ B1
);
- output X ;
- input A1 ;
- input A2 ;
- input A3 ;
- input B1 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/a31o/sky130_fd_sc_hdll__a31o_2.v b/cells/a31o/sky130_fd_sc_hdll__a31o_2.v
index d7d3a81..dff8855 100644
--- a/cells/a31o/sky130_fd_sc_hdll__a31o_2.v
+++ b/cells/a31o/sky130_fd_sc_hdll__a31o_2.v
@@ -80,26 +80,18 @@
`celldefine
module sky130_fd_sc_hdll__a31o_2 (
- X ,
- A1 ,
- A2 ,
- A3 ,
- B1 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A1,
+ A2,
+ A3,
+ B1
);
- output X ;
- input A1 ;
- input A2 ;
- input A3 ;
- input B1 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/a31o/sky130_fd_sc_hdll__a31o_4.v b/cells/a31o/sky130_fd_sc_hdll__a31o_4.v
index c7c2dd2..2962ff1 100644
--- a/cells/a31o/sky130_fd_sc_hdll__a31o_4.v
+++ b/cells/a31o/sky130_fd_sc_hdll__a31o_4.v
@@ -80,26 +80,18 @@
`celldefine
module sky130_fd_sc_hdll__a31o_4 (
- X ,
- A1 ,
- A2 ,
- A3 ,
- B1 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A1,
+ A2,
+ A3,
+ B1
);
- output X ;
- input A1 ;
- input A2 ;
- input A3 ;
- input B1 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/a31oi/sky130_fd_sc_hdll__a31oi_1.v b/cells/a31oi/sky130_fd_sc_hdll__a31oi_1.v
index ca3f01a..8b9c094 100644
--- a/cells/a31oi/sky130_fd_sc_hdll__a31oi_1.v
+++ b/cells/a31oi/sky130_fd_sc_hdll__a31oi_1.v
@@ -80,26 +80,18 @@
`celldefine
module sky130_fd_sc_hdll__a31oi_1 (
- Y ,
- A1 ,
- A2 ,
- A3 ,
- B1 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A1,
+ A2,
+ A3,
+ B1
);
- output Y ;
- input A1 ;
- input A2 ;
- input A3 ;
- input B1 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/a31oi/sky130_fd_sc_hdll__a31oi_2.v b/cells/a31oi/sky130_fd_sc_hdll__a31oi_2.v
index 55a8205..c52847d 100644
--- a/cells/a31oi/sky130_fd_sc_hdll__a31oi_2.v
+++ b/cells/a31oi/sky130_fd_sc_hdll__a31oi_2.v
@@ -80,26 +80,18 @@
`celldefine
module sky130_fd_sc_hdll__a31oi_2 (
- Y ,
- A1 ,
- A2 ,
- A3 ,
- B1 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A1,
+ A2,
+ A3,
+ B1
);
- output Y ;
- input A1 ;
- input A2 ;
- input A3 ;
- input B1 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/a31oi/sky130_fd_sc_hdll__a31oi_4.v b/cells/a31oi/sky130_fd_sc_hdll__a31oi_4.v
index 74e4943..bc4c3e7 100644
--- a/cells/a31oi/sky130_fd_sc_hdll__a31oi_4.v
+++ b/cells/a31oi/sky130_fd_sc_hdll__a31oi_4.v
@@ -80,26 +80,18 @@
`celldefine
module sky130_fd_sc_hdll__a31oi_4 (
- Y ,
- A1 ,
- A2 ,
- A3 ,
- B1 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A1,
+ A2,
+ A3,
+ B1
);
- output Y ;
- input A1 ;
- input A2 ;
- input A3 ;
- input B1 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/a32o/sky130_fd_sc_hdll__a32o_1.v b/cells/a32o/sky130_fd_sc_hdll__a32o_1.v
index a72672e..8752657 100644
--- a/cells/a32o/sky130_fd_sc_hdll__a32o_1.v
+++ b/cells/a32o/sky130_fd_sc_hdll__a32o_1.v
@@ -84,28 +84,20 @@
`celldefine
module sky130_fd_sc_hdll__a32o_1 (
- X ,
- A1 ,
- A2 ,
- A3 ,
- B1 ,
- B2 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A1,
+ A2,
+ A3,
+ B1,
+ B2
);
- output X ;
- input A1 ;
- input A2 ;
- input A3 ;
- input B1 ;
- input B2 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+ input B2;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/a32o/sky130_fd_sc_hdll__a32o_2.v b/cells/a32o/sky130_fd_sc_hdll__a32o_2.v
index bd37980..15e8042 100644
--- a/cells/a32o/sky130_fd_sc_hdll__a32o_2.v
+++ b/cells/a32o/sky130_fd_sc_hdll__a32o_2.v
@@ -84,28 +84,20 @@
`celldefine
module sky130_fd_sc_hdll__a32o_2 (
- X ,
- A1 ,
- A2 ,
- A3 ,
- B1 ,
- B2 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A1,
+ A2,
+ A3,
+ B1,
+ B2
);
- output X ;
- input A1 ;
- input A2 ;
- input A3 ;
- input B1 ;
- input B2 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+ input B2;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/a32o/sky130_fd_sc_hdll__a32o_4.v b/cells/a32o/sky130_fd_sc_hdll__a32o_4.v
index 23776ca..4284897 100644
--- a/cells/a32o/sky130_fd_sc_hdll__a32o_4.v
+++ b/cells/a32o/sky130_fd_sc_hdll__a32o_4.v
@@ -84,28 +84,20 @@
`celldefine
module sky130_fd_sc_hdll__a32o_4 (
- X ,
- A1 ,
- A2 ,
- A3 ,
- B1 ,
- B2 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A1,
+ A2,
+ A3,
+ B1,
+ B2
);
- output X ;
- input A1 ;
- input A2 ;
- input A3 ;
- input B1 ;
- input B2 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+ input B2;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/a32oi/sky130_fd_sc_hdll__a32oi_1.v b/cells/a32oi/sky130_fd_sc_hdll__a32oi_1.v
index 75f41a5..9d401cb 100644
--- a/cells/a32oi/sky130_fd_sc_hdll__a32oi_1.v
+++ b/cells/a32oi/sky130_fd_sc_hdll__a32oi_1.v
@@ -84,28 +84,20 @@
`celldefine
module sky130_fd_sc_hdll__a32oi_1 (
- Y ,
- A1 ,
- A2 ,
- A3 ,
- B1 ,
- B2 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A1,
+ A2,
+ A3,
+ B1,
+ B2
);
- output Y ;
- input A1 ;
- input A2 ;
- input A3 ;
- input B1 ;
- input B2 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+ input B2;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/a32oi/sky130_fd_sc_hdll__a32oi_2.v b/cells/a32oi/sky130_fd_sc_hdll__a32oi_2.v
index 6c54161..ddf9941 100644
--- a/cells/a32oi/sky130_fd_sc_hdll__a32oi_2.v
+++ b/cells/a32oi/sky130_fd_sc_hdll__a32oi_2.v
@@ -84,28 +84,20 @@
`celldefine
module sky130_fd_sc_hdll__a32oi_2 (
- Y ,
- A1 ,
- A2 ,
- A3 ,
- B1 ,
- B2 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A1,
+ A2,
+ A3,
+ B1,
+ B2
);
- output Y ;
- input A1 ;
- input A2 ;
- input A3 ;
- input B1 ;
- input B2 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+ input B2;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/a32oi/sky130_fd_sc_hdll__a32oi_4.v b/cells/a32oi/sky130_fd_sc_hdll__a32oi_4.v
index 020f66f..899b5df 100644
--- a/cells/a32oi/sky130_fd_sc_hdll__a32oi_4.v
+++ b/cells/a32oi/sky130_fd_sc_hdll__a32oi_4.v
@@ -84,28 +84,20 @@
`celldefine
module sky130_fd_sc_hdll__a32oi_4 (
- Y ,
- A1 ,
- A2 ,
- A3 ,
- B1 ,
- B2 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A1,
+ A2,
+ A3,
+ B1,
+ B2
);
- output Y ;
- input A1 ;
- input A2 ;
- input A3 ;
- input B1 ;
- input B2 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+ input B2;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/and2/sky130_fd_sc_hdll__and2_1.v b/cells/and2/sky130_fd_sc_hdll__and2_1.v
index 8a69287..068a992 100644
--- a/cells/and2/sky130_fd_sc_hdll__and2_1.v
+++ b/cells/and2/sky130_fd_sc_hdll__and2_1.v
@@ -72,22 +72,14 @@
`celldefine
module sky130_fd_sc_hdll__and2_1 (
- X ,
- A ,
- B ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A,
+ B
);
- output X ;
- input A ;
- input B ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
+ input B;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/and2/sky130_fd_sc_hdll__and2_2.v b/cells/and2/sky130_fd_sc_hdll__and2_2.v
index 718121b..f4f1b06 100644
--- a/cells/and2/sky130_fd_sc_hdll__and2_2.v
+++ b/cells/and2/sky130_fd_sc_hdll__and2_2.v
@@ -72,22 +72,14 @@
`celldefine
module sky130_fd_sc_hdll__and2_2 (
- X ,
- A ,
- B ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A,
+ B
);
- output X ;
- input A ;
- input B ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
+ input B;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/and2/sky130_fd_sc_hdll__and2_4.v b/cells/and2/sky130_fd_sc_hdll__and2_4.v
index e421327..307a433 100644
--- a/cells/and2/sky130_fd_sc_hdll__and2_4.v
+++ b/cells/and2/sky130_fd_sc_hdll__and2_4.v
@@ -72,22 +72,14 @@
`celldefine
module sky130_fd_sc_hdll__and2_4 (
- X ,
- A ,
- B ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A,
+ B
);
- output X ;
- input A ;
- input B ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
+ input B;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/and2/sky130_fd_sc_hdll__and2_6.v b/cells/and2/sky130_fd_sc_hdll__and2_6.v
index 5a94bf5..7ea3004 100644
--- a/cells/and2/sky130_fd_sc_hdll__and2_6.v
+++ b/cells/and2/sky130_fd_sc_hdll__and2_6.v
@@ -72,22 +72,14 @@
`celldefine
module sky130_fd_sc_hdll__and2_6 (
- X ,
- A ,
- B ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A,
+ B
);
- output X ;
- input A ;
- input B ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
+ input B;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/and2/sky130_fd_sc_hdll__and2_8.v b/cells/and2/sky130_fd_sc_hdll__and2_8.v
index 053ad70..ef1fda3 100644
--- a/cells/and2/sky130_fd_sc_hdll__and2_8.v
+++ b/cells/and2/sky130_fd_sc_hdll__and2_8.v
@@ -72,22 +72,14 @@
`celldefine
module sky130_fd_sc_hdll__and2_8 (
- X ,
- A ,
- B ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A,
+ B
);
- output X ;
- input A ;
- input B ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
+ input B;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/and2b/sky130_fd_sc_hdll__and2b_1.v b/cells/and2b/sky130_fd_sc_hdll__and2b_1.v
index 5fe3585..2d30d52 100644
--- a/cells/and2b/sky130_fd_sc_hdll__and2b_1.v
+++ b/cells/and2b/sky130_fd_sc_hdll__and2b_1.v
@@ -72,22 +72,14 @@
`celldefine
module sky130_fd_sc_hdll__and2b_1 (
- X ,
- A_N ,
- B ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A_N,
+ B
);
- output X ;
- input A_N ;
- input B ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A_N;
+ input B ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/and2b/sky130_fd_sc_hdll__and2b_2.v b/cells/and2b/sky130_fd_sc_hdll__and2b_2.v
index c7ca558..11f16a7 100644
--- a/cells/and2b/sky130_fd_sc_hdll__and2b_2.v
+++ b/cells/and2b/sky130_fd_sc_hdll__and2b_2.v
@@ -72,22 +72,14 @@
`celldefine
module sky130_fd_sc_hdll__and2b_2 (
- X ,
- A_N ,
- B ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A_N,
+ B
);
- output X ;
- input A_N ;
- input B ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A_N;
+ input B ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/and2b/sky130_fd_sc_hdll__and2b_4.v b/cells/and2b/sky130_fd_sc_hdll__and2b_4.v
index a3e671e..f9fd713 100644
--- a/cells/and2b/sky130_fd_sc_hdll__and2b_4.v
+++ b/cells/and2b/sky130_fd_sc_hdll__and2b_4.v
@@ -72,22 +72,14 @@
`celldefine
module sky130_fd_sc_hdll__and2b_4 (
- X ,
- A_N ,
- B ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A_N,
+ B
);
- output X ;
- input A_N ;
- input B ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A_N;
+ input B ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/and3/sky130_fd_sc_hdll__and3_1.v b/cells/and3/sky130_fd_sc_hdll__and3_1.v
index da630b0..469fcbf 100644
--- a/cells/and3/sky130_fd_sc_hdll__and3_1.v
+++ b/cells/and3/sky130_fd_sc_hdll__and3_1.v
@@ -75,24 +75,16 @@
`celldefine
module sky130_fd_sc_hdll__and3_1 (
- X ,
- A ,
- B ,
- C ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A,
+ B,
+ C
);
- output X ;
- input A ;
- input B ;
- input C ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
+ input B;
+ input C;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/and3/sky130_fd_sc_hdll__and3_2.v b/cells/and3/sky130_fd_sc_hdll__and3_2.v
index 703fc57..db6ca8a 100644
--- a/cells/and3/sky130_fd_sc_hdll__and3_2.v
+++ b/cells/and3/sky130_fd_sc_hdll__and3_2.v
@@ -75,24 +75,16 @@
`celldefine
module sky130_fd_sc_hdll__and3_2 (
- X ,
- A ,
- B ,
- C ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A,
+ B,
+ C
);
- output X ;
- input A ;
- input B ;
- input C ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
+ input B;
+ input C;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/and3/sky130_fd_sc_hdll__and3_4.v b/cells/and3/sky130_fd_sc_hdll__and3_4.v
index fd11871..fdcfa7b 100644
--- a/cells/and3/sky130_fd_sc_hdll__and3_4.v
+++ b/cells/and3/sky130_fd_sc_hdll__and3_4.v
@@ -75,24 +75,16 @@
`celldefine
module sky130_fd_sc_hdll__and3_4 (
- X ,
- A ,
- B ,
- C ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A,
+ B,
+ C
);
- output X ;
- input A ;
- input B ;
- input C ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
+ input B;
+ input C;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/and3b/sky130_fd_sc_hdll__and3b_1.v b/cells/and3b/sky130_fd_sc_hdll__and3b_1.v
index e46648a..0b8a4e9 100644
--- a/cells/and3b/sky130_fd_sc_hdll__and3b_1.v
+++ b/cells/and3b/sky130_fd_sc_hdll__and3b_1.v
@@ -75,24 +75,16 @@
`celldefine
module sky130_fd_sc_hdll__and3b_1 (
- X ,
- A_N ,
- B ,
- C ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A_N,
+ B ,
+ C
);
- output X ;
- input A_N ;
- input B ;
- input C ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A_N;
+ input B ;
+ input C ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/and3b/sky130_fd_sc_hdll__and3b_2.v b/cells/and3b/sky130_fd_sc_hdll__and3b_2.v
index 5256f89..0b692da 100644
--- a/cells/and3b/sky130_fd_sc_hdll__and3b_2.v
+++ b/cells/and3b/sky130_fd_sc_hdll__and3b_2.v
@@ -75,24 +75,16 @@
`celldefine
module sky130_fd_sc_hdll__and3b_2 (
- X ,
- A_N ,
- B ,
- C ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A_N,
+ B ,
+ C
);
- output X ;
- input A_N ;
- input B ;
- input C ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A_N;
+ input B ;
+ input C ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/and3b/sky130_fd_sc_hdll__and3b_4.v b/cells/and3b/sky130_fd_sc_hdll__and3b_4.v
index 4b7d915..3262ef5 100644
--- a/cells/and3b/sky130_fd_sc_hdll__and3b_4.v
+++ b/cells/and3b/sky130_fd_sc_hdll__and3b_4.v
@@ -75,24 +75,16 @@
`celldefine
module sky130_fd_sc_hdll__and3b_4 (
- X ,
- A_N ,
- B ,
- C ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A_N,
+ B ,
+ C
);
- output X ;
- input A_N ;
- input B ;
- input C ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A_N;
+ input B ;
+ input C ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/and4/sky130_fd_sc_hdll__and4_1.v b/cells/and4/sky130_fd_sc_hdll__and4_1.v
index ba91da3..cb242ea 100644
--- a/cells/and4/sky130_fd_sc_hdll__and4_1.v
+++ b/cells/and4/sky130_fd_sc_hdll__and4_1.v
@@ -78,26 +78,18 @@
`celldefine
module sky130_fd_sc_hdll__and4_1 (
- X ,
- A ,
- B ,
- C ,
- D ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A,
+ B,
+ C,
+ D
);
- output X ;
- input A ;
- input B ;
- input C ;
- input D ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
+ input B;
+ input C;
+ input D;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/and4/sky130_fd_sc_hdll__and4_2.v b/cells/and4/sky130_fd_sc_hdll__and4_2.v
index 89d1524..d8b5cd1 100644
--- a/cells/and4/sky130_fd_sc_hdll__and4_2.v
+++ b/cells/and4/sky130_fd_sc_hdll__and4_2.v
@@ -78,26 +78,18 @@
`celldefine
module sky130_fd_sc_hdll__and4_2 (
- X ,
- A ,
- B ,
- C ,
- D ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A,
+ B,
+ C,
+ D
);
- output X ;
- input A ;
- input B ;
- input C ;
- input D ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
+ input B;
+ input C;
+ input D;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/and4/sky130_fd_sc_hdll__and4_4.v b/cells/and4/sky130_fd_sc_hdll__and4_4.v
index 28d0a3a..60ffe2b 100644
--- a/cells/and4/sky130_fd_sc_hdll__and4_4.v
+++ b/cells/and4/sky130_fd_sc_hdll__and4_4.v
@@ -78,26 +78,18 @@
`celldefine
module sky130_fd_sc_hdll__and4_4 (
- X ,
- A ,
- B ,
- C ,
- D ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A,
+ B,
+ C,
+ D
);
- output X ;
- input A ;
- input B ;
- input C ;
- input D ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
+ input B;
+ input C;
+ input D;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/and4b/sky130_fd_sc_hdll__and4b_1.v b/cells/and4b/sky130_fd_sc_hdll__and4b_1.v
index 374e61a..3fae391 100644
--- a/cells/and4b/sky130_fd_sc_hdll__and4b_1.v
+++ b/cells/and4b/sky130_fd_sc_hdll__and4b_1.v
@@ -78,26 +78,18 @@
`celldefine
module sky130_fd_sc_hdll__and4b_1 (
- X ,
- A_N ,
- B ,
- C ,
- D ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A_N,
+ B ,
+ C ,
+ D
);
- output X ;
- input A_N ;
- input B ;
- input C ;
- input D ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A_N;
+ input B ;
+ input C ;
+ input D ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/and4b/sky130_fd_sc_hdll__and4b_2.v b/cells/and4b/sky130_fd_sc_hdll__and4b_2.v
index dd0605e..8076710 100644
--- a/cells/and4b/sky130_fd_sc_hdll__and4b_2.v
+++ b/cells/and4b/sky130_fd_sc_hdll__and4b_2.v
@@ -78,26 +78,18 @@
`celldefine
module sky130_fd_sc_hdll__and4b_2 (
- X ,
- A_N ,
- B ,
- C ,
- D ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A_N,
+ B ,
+ C ,
+ D
);
- output X ;
- input A_N ;
- input B ;
- input C ;
- input D ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A_N;
+ input B ;
+ input C ;
+ input D ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/and4b/sky130_fd_sc_hdll__and4b_4.v b/cells/and4b/sky130_fd_sc_hdll__and4b_4.v
index 9ed45d8..8bb5b28 100644
--- a/cells/and4b/sky130_fd_sc_hdll__and4b_4.v
+++ b/cells/and4b/sky130_fd_sc_hdll__and4b_4.v
@@ -78,26 +78,18 @@
`celldefine
module sky130_fd_sc_hdll__and4b_4 (
- X ,
- A_N ,
- B ,
- C ,
- D ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A_N,
+ B ,
+ C ,
+ D
);
- output X ;
- input A_N ;
- input B ;
- input C ;
- input D ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A_N;
+ input B ;
+ input C ;
+ input D ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/and4bb/sky130_fd_sc_hdll__and4bb_1.v b/cells/and4bb/sky130_fd_sc_hdll__and4bb_1.v
index e47bbb7..cabcaf2 100644
--- a/cells/and4bb/sky130_fd_sc_hdll__and4bb_1.v
+++ b/cells/and4bb/sky130_fd_sc_hdll__and4bb_1.v
@@ -78,26 +78,18 @@
`celldefine
module sky130_fd_sc_hdll__and4bb_1 (
- X ,
- A_N ,
- B_N ,
- C ,
- D ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A_N,
+ B_N,
+ C ,
+ D
);
- output X ;
- input A_N ;
- input B_N ;
- input C ;
- input D ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A_N;
+ input B_N;
+ input C ;
+ input D ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/and4bb/sky130_fd_sc_hdll__and4bb_2.v b/cells/and4bb/sky130_fd_sc_hdll__and4bb_2.v
index dc57a05..d6be304 100644
--- a/cells/and4bb/sky130_fd_sc_hdll__and4bb_2.v
+++ b/cells/and4bb/sky130_fd_sc_hdll__and4bb_2.v
@@ -78,26 +78,18 @@
`celldefine
module sky130_fd_sc_hdll__and4bb_2 (
- X ,
- A_N ,
- B_N ,
- C ,
- D ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A_N,
+ B_N,
+ C ,
+ D
);
- output X ;
- input A_N ;
- input B_N ;
- input C ;
- input D ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A_N;
+ input B_N;
+ input C ;
+ input D ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/and4bb/sky130_fd_sc_hdll__and4bb_4.v b/cells/and4bb/sky130_fd_sc_hdll__and4bb_4.v
index 1c359b1..fa6ba73 100644
--- a/cells/and4bb/sky130_fd_sc_hdll__and4bb_4.v
+++ b/cells/and4bb/sky130_fd_sc_hdll__and4bb_4.v
@@ -78,26 +78,18 @@
`celldefine
module sky130_fd_sc_hdll__and4bb_4 (
- X ,
- A_N ,
- B_N ,
- C ,
- D ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A_N,
+ B_N,
+ C ,
+ D
);
- output X ;
- input A_N ;
- input B_N ;
- input C ;
- input D ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A_N;
+ input B_N;
+ input C ;
+ input D ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/buf/sky130_fd_sc_hdll__buf_1.v b/cells/buf/sky130_fd_sc_hdll__buf_1.v
index 1a3db55..365f740 100644
--- a/cells/buf/sky130_fd_sc_hdll__buf_1.v
+++ b/cells/buf/sky130_fd_sc_hdll__buf_1.v
@@ -69,20 +69,12 @@
`celldefine
module sky130_fd_sc_hdll__buf_1 (
- X ,
- A ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A
);
- output X ;
- input A ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/buf/sky130_fd_sc_hdll__buf_12.v b/cells/buf/sky130_fd_sc_hdll__buf_12.v
index 016e4ff..78e58b8 100644
--- a/cells/buf/sky130_fd_sc_hdll__buf_12.v
+++ b/cells/buf/sky130_fd_sc_hdll__buf_12.v
@@ -69,20 +69,12 @@
`celldefine
module sky130_fd_sc_hdll__buf_12 (
- X ,
- A ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A
);
- output X ;
- input A ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/buf/sky130_fd_sc_hdll__buf_16.v b/cells/buf/sky130_fd_sc_hdll__buf_16.v
index 515bd9e..169b7f9 100644
--- a/cells/buf/sky130_fd_sc_hdll__buf_16.v
+++ b/cells/buf/sky130_fd_sc_hdll__buf_16.v
@@ -69,20 +69,12 @@
`celldefine
module sky130_fd_sc_hdll__buf_16 (
- X ,
- A ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A
);
- output X ;
- input A ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/buf/sky130_fd_sc_hdll__buf_2.v b/cells/buf/sky130_fd_sc_hdll__buf_2.v
index f60b9e3..6a32a7b 100644
--- a/cells/buf/sky130_fd_sc_hdll__buf_2.v
+++ b/cells/buf/sky130_fd_sc_hdll__buf_2.v
@@ -69,20 +69,12 @@
`celldefine
module sky130_fd_sc_hdll__buf_2 (
- X ,
- A ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A
);
- output X ;
- input A ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/buf/sky130_fd_sc_hdll__buf_4.v b/cells/buf/sky130_fd_sc_hdll__buf_4.v
index 4c472d7..77f8a5a 100644
--- a/cells/buf/sky130_fd_sc_hdll__buf_4.v
+++ b/cells/buf/sky130_fd_sc_hdll__buf_4.v
@@ -69,20 +69,12 @@
`celldefine
module sky130_fd_sc_hdll__buf_4 (
- X ,
- A ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A
);
- output X ;
- input A ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/buf/sky130_fd_sc_hdll__buf_6.v b/cells/buf/sky130_fd_sc_hdll__buf_6.v
index 6b4f833..c7f879b 100644
--- a/cells/buf/sky130_fd_sc_hdll__buf_6.v
+++ b/cells/buf/sky130_fd_sc_hdll__buf_6.v
@@ -69,20 +69,12 @@
`celldefine
module sky130_fd_sc_hdll__buf_6 (
- X ,
- A ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A
);
- output X ;
- input A ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/buf/sky130_fd_sc_hdll__buf_8.v b/cells/buf/sky130_fd_sc_hdll__buf_8.v
index d38665f..7f19ba5 100644
--- a/cells/buf/sky130_fd_sc_hdll__buf_8.v
+++ b/cells/buf/sky130_fd_sc_hdll__buf_8.v
@@ -69,20 +69,12 @@
`celldefine
module sky130_fd_sc_hdll__buf_8 (
- X ,
- A ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A
);
- output X ;
- input A ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/bufbuf/sky130_fd_sc_hdll__bufbuf_16.v b/cells/bufbuf/sky130_fd_sc_hdll__bufbuf_16.v
index 41e1667..3cae647 100644
--- a/cells/bufbuf/sky130_fd_sc_hdll__bufbuf_16.v
+++ b/cells/bufbuf/sky130_fd_sc_hdll__bufbuf_16.v
@@ -69,20 +69,12 @@
`celldefine
module sky130_fd_sc_hdll__bufbuf_16 (
- X ,
- A ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A
);
- output X ;
- input A ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/bufbuf/sky130_fd_sc_hdll__bufbuf_8.v b/cells/bufbuf/sky130_fd_sc_hdll__bufbuf_8.v
index 9ca2f16..d896184 100644
--- a/cells/bufbuf/sky130_fd_sc_hdll__bufbuf_8.v
+++ b/cells/bufbuf/sky130_fd_sc_hdll__bufbuf_8.v
@@ -69,20 +69,12 @@
`celldefine
module sky130_fd_sc_hdll__bufbuf_8 (
- X ,
- A ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A
);
- output X ;
- input A ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/bufinv/sky130_fd_sc_hdll__bufinv_16.v b/cells/bufinv/sky130_fd_sc_hdll__bufinv_16.v
index 3658092..4f34f00 100644
--- a/cells/bufinv/sky130_fd_sc_hdll__bufinv_16.v
+++ b/cells/bufinv/sky130_fd_sc_hdll__bufinv_16.v
@@ -69,20 +69,12 @@
`celldefine
module sky130_fd_sc_hdll__bufinv_16 (
- Y ,
- A ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A
);
- output Y ;
- input A ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/bufinv/sky130_fd_sc_hdll__bufinv_8.v b/cells/bufinv/sky130_fd_sc_hdll__bufinv_8.v
index e368e19..945a966 100644
--- a/cells/bufinv/sky130_fd_sc_hdll__bufinv_8.v
+++ b/cells/bufinv/sky130_fd_sc_hdll__bufinv_8.v
@@ -69,20 +69,12 @@
`celldefine
module sky130_fd_sc_hdll__bufinv_8 (
- Y ,
- A ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A
);
- output Y ;
- input A ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/clkbuf/sky130_fd_sc_hdll__clkbuf_1.v b/cells/clkbuf/sky130_fd_sc_hdll__clkbuf_1.v
index f78339b..5526231 100644
--- a/cells/clkbuf/sky130_fd_sc_hdll__clkbuf_1.v
+++ b/cells/clkbuf/sky130_fd_sc_hdll__clkbuf_1.v
@@ -69,20 +69,12 @@
`celldefine
module sky130_fd_sc_hdll__clkbuf_1 (
- X ,
- A ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A
);
- output X ;
- input A ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/clkbuf/sky130_fd_sc_hdll__clkbuf_12.v b/cells/clkbuf/sky130_fd_sc_hdll__clkbuf_12.v
index 375aec4..cf39110 100644
--- a/cells/clkbuf/sky130_fd_sc_hdll__clkbuf_12.v
+++ b/cells/clkbuf/sky130_fd_sc_hdll__clkbuf_12.v
@@ -69,20 +69,12 @@
`celldefine
module sky130_fd_sc_hdll__clkbuf_12 (
- X ,
- A ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A
);
- output X ;
- input A ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/clkbuf/sky130_fd_sc_hdll__clkbuf_16.v b/cells/clkbuf/sky130_fd_sc_hdll__clkbuf_16.v
index 3352bfb..585ad82 100644
--- a/cells/clkbuf/sky130_fd_sc_hdll__clkbuf_16.v
+++ b/cells/clkbuf/sky130_fd_sc_hdll__clkbuf_16.v
@@ -69,20 +69,12 @@
`celldefine
module sky130_fd_sc_hdll__clkbuf_16 (
- X ,
- A ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A
);
- output X ;
- input A ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/clkbuf/sky130_fd_sc_hdll__clkbuf_2.v b/cells/clkbuf/sky130_fd_sc_hdll__clkbuf_2.v
index a80e84a..13d5e96 100644
--- a/cells/clkbuf/sky130_fd_sc_hdll__clkbuf_2.v
+++ b/cells/clkbuf/sky130_fd_sc_hdll__clkbuf_2.v
@@ -69,20 +69,12 @@
`celldefine
module sky130_fd_sc_hdll__clkbuf_2 (
- X ,
- A ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A
);
- output X ;
- input A ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/clkbuf/sky130_fd_sc_hdll__clkbuf_4.v b/cells/clkbuf/sky130_fd_sc_hdll__clkbuf_4.v
index 154ab46..422524b 100644
--- a/cells/clkbuf/sky130_fd_sc_hdll__clkbuf_4.v
+++ b/cells/clkbuf/sky130_fd_sc_hdll__clkbuf_4.v
@@ -69,20 +69,12 @@
`celldefine
module sky130_fd_sc_hdll__clkbuf_4 (
- X ,
- A ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A
);
- output X ;
- input A ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/clkbuf/sky130_fd_sc_hdll__clkbuf_6.v b/cells/clkbuf/sky130_fd_sc_hdll__clkbuf_6.v
index 49b732d..c7b7b31 100644
--- a/cells/clkbuf/sky130_fd_sc_hdll__clkbuf_6.v
+++ b/cells/clkbuf/sky130_fd_sc_hdll__clkbuf_6.v
@@ -69,20 +69,12 @@
`celldefine
module sky130_fd_sc_hdll__clkbuf_6 (
- X ,
- A ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A
);
- output X ;
- input A ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/clkbuf/sky130_fd_sc_hdll__clkbuf_8.v b/cells/clkbuf/sky130_fd_sc_hdll__clkbuf_8.v
index 999db5b..18c3e29 100644
--- a/cells/clkbuf/sky130_fd_sc_hdll__clkbuf_8.v
+++ b/cells/clkbuf/sky130_fd_sc_hdll__clkbuf_8.v
@@ -69,20 +69,12 @@
`celldefine
module sky130_fd_sc_hdll__clkbuf_8 (
- X ,
- A ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A
);
- output X ;
- input A ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/clkinv/sky130_fd_sc_hdll__clkinv_1.v b/cells/clkinv/sky130_fd_sc_hdll__clkinv_1.v
index e897022..171348f 100644
--- a/cells/clkinv/sky130_fd_sc_hdll__clkinv_1.v
+++ b/cells/clkinv/sky130_fd_sc_hdll__clkinv_1.v
@@ -69,20 +69,12 @@
`celldefine
module sky130_fd_sc_hdll__clkinv_1 (
- Y ,
- A ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A
);
- output Y ;
- input A ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/clkinv/sky130_fd_sc_hdll__clkinv_12.v b/cells/clkinv/sky130_fd_sc_hdll__clkinv_12.v
index 22856c7..6618a8a 100644
--- a/cells/clkinv/sky130_fd_sc_hdll__clkinv_12.v
+++ b/cells/clkinv/sky130_fd_sc_hdll__clkinv_12.v
@@ -69,20 +69,12 @@
`celldefine
module sky130_fd_sc_hdll__clkinv_12 (
- Y ,
- A ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A
);
- output Y ;
- input A ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/clkinv/sky130_fd_sc_hdll__clkinv_16.v b/cells/clkinv/sky130_fd_sc_hdll__clkinv_16.v
index 5777d2b..c0230af 100644
--- a/cells/clkinv/sky130_fd_sc_hdll__clkinv_16.v
+++ b/cells/clkinv/sky130_fd_sc_hdll__clkinv_16.v
@@ -69,20 +69,12 @@
`celldefine
module sky130_fd_sc_hdll__clkinv_16 (
- Y ,
- A ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A
);
- output Y ;
- input A ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/clkinv/sky130_fd_sc_hdll__clkinv_2.v b/cells/clkinv/sky130_fd_sc_hdll__clkinv_2.v
index 5237195..c6d9226 100644
--- a/cells/clkinv/sky130_fd_sc_hdll__clkinv_2.v
+++ b/cells/clkinv/sky130_fd_sc_hdll__clkinv_2.v
@@ -69,20 +69,12 @@
`celldefine
module sky130_fd_sc_hdll__clkinv_2 (
- Y ,
- A ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A
);
- output Y ;
- input A ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/clkinv/sky130_fd_sc_hdll__clkinv_4.v b/cells/clkinv/sky130_fd_sc_hdll__clkinv_4.v
index aaf9802..efb98ae 100644
--- a/cells/clkinv/sky130_fd_sc_hdll__clkinv_4.v
+++ b/cells/clkinv/sky130_fd_sc_hdll__clkinv_4.v
@@ -69,20 +69,12 @@
`celldefine
module sky130_fd_sc_hdll__clkinv_4 (
- Y ,
- A ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A
);
- output Y ;
- input A ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/clkinv/sky130_fd_sc_hdll__clkinv_8.v b/cells/clkinv/sky130_fd_sc_hdll__clkinv_8.v
index db8c79e..7035fb7 100644
--- a/cells/clkinv/sky130_fd_sc_hdll__clkinv_8.v
+++ b/cells/clkinv/sky130_fd_sc_hdll__clkinv_8.v
@@ -69,20 +69,12 @@
`celldefine
module sky130_fd_sc_hdll__clkinv_8 (
- Y ,
- A ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A
);
- output Y ;
- input A ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/clkinvlp/sky130_fd_sc_hdll__clkinvlp_2.v b/cells/clkinvlp/sky130_fd_sc_hdll__clkinvlp_2.v
index 57ca147..235355b 100644
--- a/cells/clkinvlp/sky130_fd_sc_hdll__clkinvlp_2.v
+++ b/cells/clkinvlp/sky130_fd_sc_hdll__clkinvlp_2.v
@@ -69,20 +69,12 @@
`celldefine
module sky130_fd_sc_hdll__clkinvlp_2 (
- Y ,
- A ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A
);
- output Y ;
- input A ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/clkinvlp/sky130_fd_sc_hdll__clkinvlp_4.v b/cells/clkinvlp/sky130_fd_sc_hdll__clkinvlp_4.v
index 3106c57..9c8fb5e 100644
--- a/cells/clkinvlp/sky130_fd_sc_hdll__clkinvlp_4.v
+++ b/cells/clkinvlp/sky130_fd_sc_hdll__clkinvlp_4.v
@@ -69,20 +69,12 @@
`celldefine
module sky130_fd_sc_hdll__clkinvlp_4 (
- Y ,
- A ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A
);
- output Y ;
- input A ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/clkmux2/sky130_fd_sc_hdll__clkmux2_1.v b/cells/clkmux2/sky130_fd_sc_hdll__clkmux2_1.v
index 00f1b27..654817e 100644
--- a/cells/clkmux2/sky130_fd_sc_hdll__clkmux2_1.v
+++ b/cells/clkmux2/sky130_fd_sc_hdll__clkmux2_1.v
@@ -75,24 +75,16 @@
`celldefine
module sky130_fd_sc_hdll__clkmux2_1 (
- X ,
- A0 ,
- A1 ,
- S ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A0,
+ A1,
+ S
);
- output X ;
- input A0 ;
- input A1 ;
- input S ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A0;
+ input A1;
+ input S ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/clkmux2/sky130_fd_sc_hdll__clkmux2_2.v b/cells/clkmux2/sky130_fd_sc_hdll__clkmux2_2.v
index 1220f4b..c67ee1d 100644
--- a/cells/clkmux2/sky130_fd_sc_hdll__clkmux2_2.v
+++ b/cells/clkmux2/sky130_fd_sc_hdll__clkmux2_2.v
@@ -75,24 +75,16 @@
`celldefine
module sky130_fd_sc_hdll__clkmux2_2 (
- X ,
- A0 ,
- A1 ,
- S ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A0,
+ A1,
+ S
);
- output X ;
- input A0 ;
- input A1 ;
- input S ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A0;
+ input A1;
+ input S ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/clkmux2/sky130_fd_sc_hdll__clkmux2_4.v b/cells/clkmux2/sky130_fd_sc_hdll__clkmux2_4.v
index 830a23b..2952c09 100644
--- a/cells/clkmux2/sky130_fd_sc_hdll__clkmux2_4.v
+++ b/cells/clkmux2/sky130_fd_sc_hdll__clkmux2_4.v
@@ -75,24 +75,16 @@
`celldefine
module sky130_fd_sc_hdll__clkmux2_4 (
- X ,
- A0 ,
- A1 ,
- S ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A0,
+ A1,
+ S
);
- output X ;
- input A0 ;
- input A1 ;
- input S ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A0;
+ input A1;
+ input S ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/conb/sky130_fd_sc_hdll__conb_1.v b/cells/conb/sky130_fd_sc_hdll__conb_1.v
index 160dbfd..7d98832 100644
--- a/cells/conb/sky130_fd_sc_hdll__conb_1.v
+++ b/cells/conb/sky130_fd_sc_hdll__conb_1.v
@@ -69,20 +69,12 @@
`celldefine
module sky130_fd_sc_hdll__conb_1 (
- HI ,
- LO ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ HI,
+ LO
);
- output HI ;
- output LO ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output HI;
+ output LO;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/decap/sky130_fd_sc_hdll__decap_12.v b/cells/decap/sky130_fd_sc_hdll__decap_12.v
index 3dfa660..1fe3c33 100644
--- a/cells/decap/sky130_fd_sc_hdll__decap_12.v
+++ b/cells/decap/sky130_fd_sc_hdll__decap_12.v
@@ -62,18 +62,7 @@
/*********************************************************/
`celldefine
-module sky130_fd_sc_hdll__decap_12 (
- VPWR,
- VGND,
- VPB ,
- VNB
-);
-
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
-
+module sky130_fd_sc_hdll__decap_12 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
diff --git a/cells/decap/sky130_fd_sc_hdll__decap_3.v b/cells/decap/sky130_fd_sc_hdll__decap_3.v
index 549027c..2292136 100644
--- a/cells/decap/sky130_fd_sc_hdll__decap_3.v
+++ b/cells/decap/sky130_fd_sc_hdll__decap_3.v
@@ -62,18 +62,7 @@
/*********************************************************/
`celldefine
-module sky130_fd_sc_hdll__decap_3 (
- VPWR,
- VGND,
- VPB ,
- VNB
-);
-
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
-
+module sky130_fd_sc_hdll__decap_3 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
diff --git a/cells/decap/sky130_fd_sc_hdll__decap_4.v b/cells/decap/sky130_fd_sc_hdll__decap_4.v
index a1d7dc7..8b30354 100644
--- a/cells/decap/sky130_fd_sc_hdll__decap_4.v
+++ b/cells/decap/sky130_fd_sc_hdll__decap_4.v
@@ -62,18 +62,7 @@
/*********************************************************/
`celldefine
-module sky130_fd_sc_hdll__decap_4 (
- VPWR,
- VGND,
- VPB ,
- VNB
-);
-
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
-
+module sky130_fd_sc_hdll__decap_4 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
diff --git a/cells/decap/sky130_fd_sc_hdll__decap_6.v b/cells/decap/sky130_fd_sc_hdll__decap_6.v
index 7d63d36..c76ae7e 100644
--- a/cells/decap/sky130_fd_sc_hdll__decap_6.v
+++ b/cells/decap/sky130_fd_sc_hdll__decap_6.v
@@ -62,18 +62,7 @@
/*********************************************************/
`celldefine
-module sky130_fd_sc_hdll__decap_6 (
- VPWR,
- VGND,
- VPB ,
- VNB
-);
-
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
-
+module sky130_fd_sc_hdll__decap_6 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
diff --git a/cells/decap/sky130_fd_sc_hdll__decap_8.v b/cells/decap/sky130_fd_sc_hdll__decap_8.v
index f8fe0b7..9bfa7e9 100644
--- a/cells/decap/sky130_fd_sc_hdll__decap_8.v
+++ b/cells/decap/sky130_fd_sc_hdll__decap_8.v
@@ -62,18 +62,7 @@
/*********************************************************/
`celldefine
-module sky130_fd_sc_hdll__decap_8 (
- VPWR,
- VGND,
- VPB ,
- VNB
-);
-
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
-
+module sky130_fd_sc_hdll__decap_8 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
diff --git a/cells/dfrtp/sky130_fd_sc_hdll__dfrtp_1.v b/cells/dfrtp/sky130_fd_sc_hdll__dfrtp_1.v
index cad33b7..1f4f84a 100644
--- a/cells/dfrtp/sky130_fd_sc_hdll__dfrtp_1.v
+++ b/cells/dfrtp/sky130_fd_sc_hdll__dfrtp_1.v
@@ -78,21 +78,13 @@
Q ,
CLK ,
D ,
- RESET_B,
- VPWR ,
- VGND ,
- VPB ,
- VNB
+ RESET_B
);
output Q ;
input CLK ;
input D ;
input RESET_B;
- input VPWR ;
- input VGND ;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/dfrtp/sky130_fd_sc_hdll__dfrtp_2.v b/cells/dfrtp/sky130_fd_sc_hdll__dfrtp_2.v
index fa23db7..00b82e8 100644
--- a/cells/dfrtp/sky130_fd_sc_hdll__dfrtp_2.v
+++ b/cells/dfrtp/sky130_fd_sc_hdll__dfrtp_2.v
@@ -78,21 +78,13 @@
Q ,
CLK ,
D ,
- RESET_B,
- VPWR ,
- VGND ,
- VPB ,
- VNB
+ RESET_B
);
output Q ;
input CLK ;
input D ;
input RESET_B;
- input VPWR ;
- input VGND ;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/dfrtp/sky130_fd_sc_hdll__dfrtp_4.v b/cells/dfrtp/sky130_fd_sc_hdll__dfrtp_4.v
index e563d96..2a8e0f2 100644
--- a/cells/dfrtp/sky130_fd_sc_hdll__dfrtp_4.v
+++ b/cells/dfrtp/sky130_fd_sc_hdll__dfrtp_4.v
@@ -78,21 +78,13 @@
Q ,
CLK ,
D ,
- RESET_B,
- VPWR ,
- VGND ,
- VPB ,
- VNB
+ RESET_B
);
output Q ;
input CLK ;
input D ;
input RESET_B;
- input VPWR ;
- input VGND ;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/dfstp/sky130_fd_sc_hdll__dfstp_1.v b/cells/dfstp/sky130_fd_sc_hdll__dfstp_1.v
index c789767..b7f3cb6 100644
--- a/cells/dfstp/sky130_fd_sc_hdll__dfstp_1.v
+++ b/cells/dfstp/sky130_fd_sc_hdll__dfstp_1.v
@@ -78,21 +78,13 @@
Q ,
CLK ,
D ,
- SET_B,
- VPWR ,
- VGND ,
- VPB ,
- VNB
+ SET_B
);
output Q ;
input CLK ;
input D ;
input SET_B;
- input VPWR ;
- input VGND ;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/dfstp/sky130_fd_sc_hdll__dfstp_2.v b/cells/dfstp/sky130_fd_sc_hdll__dfstp_2.v
index 79b4ff6..e8141c1 100644
--- a/cells/dfstp/sky130_fd_sc_hdll__dfstp_2.v
+++ b/cells/dfstp/sky130_fd_sc_hdll__dfstp_2.v
@@ -78,21 +78,13 @@
Q ,
CLK ,
D ,
- SET_B,
- VPWR ,
- VGND ,
- VPB ,
- VNB
+ SET_B
);
output Q ;
input CLK ;
input D ;
input SET_B;
- input VPWR ;
- input VGND ;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/dfstp/sky130_fd_sc_hdll__dfstp_4.v b/cells/dfstp/sky130_fd_sc_hdll__dfstp_4.v
index f25e3ee..78259a5 100644
--- a/cells/dfstp/sky130_fd_sc_hdll__dfstp_4.v
+++ b/cells/dfstp/sky130_fd_sc_hdll__dfstp_4.v
@@ -78,21 +78,13 @@
Q ,
CLK ,
D ,
- SET_B,
- VPWR ,
- VGND ,
- VPB ,
- VNB
+ SET_B
);
output Q ;
input CLK ;
input D ;
input SET_B;
- input VPWR ;
- input VGND ;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/diode/sky130_fd_sc_hdll__diode_2.v b/cells/diode/sky130_fd_sc_hdll__diode_2.v
index 0b7298b..8a04df0 100644
--- a/cells/diode/sky130_fd_sc_hdll__diode_2.v
+++ b/cells/diode/sky130_fd_sc_hdll__diode_2.v
@@ -66,18 +66,10 @@
`celldefine
module sky130_fd_sc_hdll__diode_2 (
- DIODE,
- VPWR ,
- VGND ,
- VPB ,
- VNB
+ DIODE
);
input DIODE;
- input VPWR ;
- input VGND ;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/diode/sky130_fd_sc_hdll__diode_4.v b/cells/diode/sky130_fd_sc_hdll__diode_4.v
index d9df9e0..cc45c7c 100644
--- a/cells/diode/sky130_fd_sc_hdll__diode_4.v
+++ b/cells/diode/sky130_fd_sc_hdll__diode_4.v
@@ -66,18 +66,10 @@
`celldefine
module sky130_fd_sc_hdll__diode_4 (
- DIODE,
- VPWR ,
- VGND ,
- VPB ,
- VNB
+ DIODE
);
input DIODE;
- input VPWR ;
- input VGND ;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/diode/sky130_fd_sc_hdll__diode_6.v b/cells/diode/sky130_fd_sc_hdll__diode_6.v
index 37aa616..82c0c5b 100644
--- a/cells/diode/sky130_fd_sc_hdll__diode_6.v
+++ b/cells/diode/sky130_fd_sc_hdll__diode_6.v
@@ -66,18 +66,10 @@
`celldefine
module sky130_fd_sc_hdll__diode_6 (
- DIODE,
- VPWR ,
- VGND ,
- VPB ,
- VNB
+ DIODE
);
input DIODE;
- input VPWR ;
- input VGND ;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/diode/sky130_fd_sc_hdll__diode_8.v b/cells/diode/sky130_fd_sc_hdll__diode_8.v
index 2145a94..c323922 100644
--- a/cells/diode/sky130_fd_sc_hdll__diode_8.v
+++ b/cells/diode/sky130_fd_sc_hdll__diode_8.v
@@ -66,18 +66,10 @@
`celldefine
module sky130_fd_sc_hdll__diode_8 (
- DIODE,
- VPWR ,
- VGND ,
- VPB ,
- VNB
+ DIODE
);
input DIODE;
- input VPWR ;
- input VGND ;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/dlrtn/sky130_fd_sc_hdll__dlrtn_1.v b/cells/dlrtn/sky130_fd_sc_hdll__dlrtn_1.v
index 2163572..6a755ce 100644
--- a/cells/dlrtn/sky130_fd_sc_hdll__dlrtn_1.v
+++ b/cells/dlrtn/sky130_fd_sc_hdll__dlrtn_1.v
@@ -78,21 +78,13 @@
Q ,
RESET_B,
D ,
- GATE_N ,
- VPWR ,
- VGND ,
- VPB ,
- VNB
+ GATE_N
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
- input VPWR ;
- input VGND ;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/dlrtn/sky130_fd_sc_hdll__dlrtn_2.v b/cells/dlrtn/sky130_fd_sc_hdll__dlrtn_2.v
index f349c5a..ddf814b 100644
--- a/cells/dlrtn/sky130_fd_sc_hdll__dlrtn_2.v
+++ b/cells/dlrtn/sky130_fd_sc_hdll__dlrtn_2.v
@@ -78,21 +78,13 @@
Q ,
RESET_B,
D ,
- GATE_N ,
- VPWR ,
- VGND ,
- VPB ,
- VNB
+ GATE_N
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
- input VPWR ;
- input VGND ;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/dlrtn/sky130_fd_sc_hdll__dlrtn_4.v b/cells/dlrtn/sky130_fd_sc_hdll__dlrtn_4.v
index f6e3463..056dc63 100644
--- a/cells/dlrtn/sky130_fd_sc_hdll__dlrtn_4.v
+++ b/cells/dlrtn/sky130_fd_sc_hdll__dlrtn_4.v
@@ -78,21 +78,13 @@
Q ,
RESET_B,
D ,
- GATE_N ,
- VPWR ,
- VGND ,
- VPB ,
- VNB
+ GATE_N
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
- input VPWR ;
- input VGND ;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/dlrtp/sky130_fd_sc_hdll__dlrtp_1.v b/cells/dlrtp/sky130_fd_sc_hdll__dlrtp_1.v
index 860b7d8..3b9194d 100644
--- a/cells/dlrtp/sky130_fd_sc_hdll__dlrtp_1.v
+++ b/cells/dlrtp/sky130_fd_sc_hdll__dlrtp_1.v
@@ -79,21 +79,13 @@
Q ,
RESET_B,
D ,
- GATE ,
- VPWR ,
- VGND ,
- VPB ,
- VNB
+ GATE
);
output Q ;
input RESET_B;
input D ;
input GATE ;
- input VPWR ;
- input VGND ;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/dlrtp/sky130_fd_sc_hdll__dlrtp_2.v b/cells/dlrtp/sky130_fd_sc_hdll__dlrtp_2.v
index 7125d90..ea82caf 100644
--- a/cells/dlrtp/sky130_fd_sc_hdll__dlrtp_2.v
+++ b/cells/dlrtp/sky130_fd_sc_hdll__dlrtp_2.v
@@ -79,21 +79,13 @@
Q ,
RESET_B,
D ,
- GATE ,
- VPWR ,
- VGND ,
- VPB ,
- VNB
+ GATE
);
output Q ;
input RESET_B;
input D ;
input GATE ;
- input VPWR ;
- input VGND ;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/dlrtp/sky130_fd_sc_hdll__dlrtp_4.v b/cells/dlrtp/sky130_fd_sc_hdll__dlrtp_4.v
index a91043b..21bf118 100644
--- a/cells/dlrtp/sky130_fd_sc_hdll__dlrtp_4.v
+++ b/cells/dlrtp/sky130_fd_sc_hdll__dlrtp_4.v
@@ -79,21 +79,13 @@
Q ,
RESET_B,
D ,
- GATE ,
- VPWR ,
- VGND ,
- VPB ,
- VNB
+ GATE
);
output Q ;
input RESET_B;
input D ;
input GATE ;
- input VPWR ;
- input VGND ;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/dlxtn/sky130_fd_sc_hdll__dlxtn_1.v b/cells/dlxtn/sky130_fd_sc_hdll__dlxtn_1.v
index 8f13e00..69a59c2 100644
--- a/cells/dlxtn/sky130_fd_sc_hdll__dlxtn_1.v
+++ b/cells/dlxtn/sky130_fd_sc_hdll__dlxtn_1.v
@@ -74,20 +74,12 @@
module sky130_fd_sc_hdll__dlxtn_1 (
Q ,
D ,
- GATE_N,
- VPWR ,
- VGND ,
- VPB ,
- VNB
+ GATE_N
);
output Q ;
input D ;
input GATE_N;
- input VPWR ;
- input VGND ;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/dlxtn/sky130_fd_sc_hdll__dlxtn_2.v b/cells/dlxtn/sky130_fd_sc_hdll__dlxtn_2.v
index 80c00ef..dd3825a 100644
--- a/cells/dlxtn/sky130_fd_sc_hdll__dlxtn_2.v
+++ b/cells/dlxtn/sky130_fd_sc_hdll__dlxtn_2.v
@@ -74,20 +74,12 @@
module sky130_fd_sc_hdll__dlxtn_2 (
Q ,
D ,
- GATE_N,
- VPWR ,
- VGND ,
- VPB ,
- VNB
+ GATE_N
);
output Q ;
input D ;
input GATE_N;
- input VPWR ;
- input VGND ;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/dlxtn/sky130_fd_sc_hdll__dlxtn_4.v b/cells/dlxtn/sky130_fd_sc_hdll__dlxtn_4.v
index a649151..8644a9f 100644
--- a/cells/dlxtn/sky130_fd_sc_hdll__dlxtn_4.v
+++ b/cells/dlxtn/sky130_fd_sc_hdll__dlxtn_4.v
@@ -74,20 +74,12 @@
module sky130_fd_sc_hdll__dlxtn_4 (
Q ,
D ,
- GATE_N,
- VPWR ,
- VGND ,
- VPB ,
- VNB
+ GATE_N
);
output Q ;
input D ;
input GATE_N;
- input VPWR ;
- input VGND ;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/dlygate4sd1/sky130_fd_sc_hdll__dlygate4sd1_1.v b/cells/dlygate4sd1/sky130_fd_sc_hdll__dlygate4sd1_1.v
index b70be0c..a26f834 100644
--- a/cells/dlygate4sd1/sky130_fd_sc_hdll__dlygate4sd1_1.v
+++ b/cells/dlygate4sd1/sky130_fd_sc_hdll__dlygate4sd1_1.v
@@ -69,20 +69,12 @@
`celldefine
module sky130_fd_sc_hdll__dlygate4sd1_1 (
- X ,
- A ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A
);
- output X ;
- input A ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/dlygate4sd2/sky130_fd_sc_hdll__dlygate4sd2_1.v b/cells/dlygate4sd2/sky130_fd_sc_hdll__dlygate4sd2_1.v
index 85d630d..de973ce 100644
--- a/cells/dlygate4sd2/sky130_fd_sc_hdll__dlygate4sd2_1.v
+++ b/cells/dlygate4sd2/sky130_fd_sc_hdll__dlygate4sd2_1.v
@@ -69,20 +69,12 @@
`celldefine
module sky130_fd_sc_hdll__dlygate4sd2_1 (
- X ,
- A ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A
);
- output X ;
- input A ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/dlygate4sd3/sky130_fd_sc_hdll__dlygate4sd3_1.v b/cells/dlygate4sd3/sky130_fd_sc_hdll__dlygate4sd3_1.v
index af923a0..577691b 100644
--- a/cells/dlygate4sd3/sky130_fd_sc_hdll__dlygate4sd3_1.v
+++ b/cells/dlygate4sd3/sky130_fd_sc_hdll__dlygate4sd3_1.v
@@ -69,20 +69,12 @@
`celldefine
module sky130_fd_sc_hdll__dlygate4sd3_1 (
- X ,
- A ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A
);
- output X ;
- input A ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/ebufn/sky130_fd_sc_hdll__ebufn_1.v b/cells/ebufn/sky130_fd_sc_hdll__ebufn_1.v
index 1e33c21..bba2b57 100644
--- a/cells/ebufn/sky130_fd_sc_hdll__ebufn_1.v
+++ b/cells/ebufn/sky130_fd_sc_hdll__ebufn_1.v
@@ -74,20 +74,12 @@
module sky130_fd_sc_hdll__ebufn_1 (
Z ,
A ,
- TE_B,
- VPWR,
- VGND,
- VPB ,
- VNB
+ TE_B
);
output Z ;
input A ;
input TE_B;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/ebufn/sky130_fd_sc_hdll__ebufn_2.v b/cells/ebufn/sky130_fd_sc_hdll__ebufn_2.v
index c354824..8caac5d 100644
--- a/cells/ebufn/sky130_fd_sc_hdll__ebufn_2.v
+++ b/cells/ebufn/sky130_fd_sc_hdll__ebufn_2.v
@@ -74,20 +74,12 @@
module sky130_fd_sc_hdll__ebufn_2 (
Z ,
A ,
- TE_B,
- VPWR,
- VGND,
- VPB ,
- VNB
+ TE_B
);
output Z ;
input A ;
input TE_B;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/ebufn/sky130_fd_sc_hdll__ebufn_4.v b/cells/ebufn/sky130_fd_sc_hdll__ebufn_4.v
index 3b5955c..97e39b1 100644
--- a/cells/ebufn/sky130_fd_sc_hdll__ebufn_4.v
+++ b/cells/ebufn/sky130_fd_sc_hdll__ebufn_4.v
@@ -74,20 +74,12 @@
module sky130_fd_sc_hdll__ebufn_4 (
Z ,
A ,
- TE_B,
- VPWR,
- VGND,
- VPB ,
- VNB
+ TE_B
);
output Z ;
input A ;
input TE_B;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/ebufn/sky130_fd_sc_hdll__ebufn_8.v b/cells/ebufn/sky130_fd_sc_hdll__ebufn_8.v
index a2e56ae..2fff26d 100644
--- a/cells/ebufn/sky130_fd_sc_hdll__ebufn_8.v
+++ b/cells/ebufn/sky130_fd_sc_hdll__ebufn_8.v
@@ -74,20 +74,12 @@
module sky130_fd_sc_hdll__ebufn_8 (
Z ,
A ,
- TE_B,
- VPWR,
- VGND,
- VPB ,
- VNB
+ TE_B
);
output Z ;
input A ;
input TE_B;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/einvn/sky130_fd_sc_hdll__einvn_1.v b/cells/einvn/sky130_fd_sc_hdll__einvn_1.v
index 4533d6c..1956eba 100644
--- a/cells/einvn/sky130_fd_sc_hdll__einvn_1.v
+++ b/cells/einvn/sky130_fd_sc_hdll__einvn_1.v
@@ -74,20 +74,12 @@
module sky130_fd_sc_hdll__einvn_1 (
Z ,
A ,
- TE_B,
- VPWR,
- VGND,
- VPB ,
- VNB
+ TE_B
);
output Z ;
input A ;
input TE_B;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/einvn/sky130_fd_sc_hdll__einvn_2.v b/cells/einvn/sky130_fd_sc_hdll__einvn_2.v
index 42b9e09..2881a40 100644
--- a/cells/einvn/sky130_fd_sc_hdll__einvn_2.v
+++ b/cells/einvn/sky130_fd_sc_hdll__einvn_2.v
@@ -74,20 +74,12 @@
module sky130_fd_sc_hdll__einvn_2 (
Z ,
A ,
- TE_B,
- VPWR,
- VGND,
- VPB ,
- VNB
+ TE_B
);
output Z ;
input A ;
input TE_B;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/einvn/sky130_fd_sc_hdll__einvn_4.v b/cells/einvn/sky130_fd_sc_hdll__einvn_4.v
index 8313649..c7cfb37 100644
--- a/cells/einvn/sky130_fd_sc_hdll__einvn_4.v
+++ b/cells/einvn/sky130_fd_sc_hdll__einvn_4.v
@@ -74,20 +74,12 @@
module sky130_fd_sc_hdll__einvn_4 (
Z ,
A ,
- TE_B,
- VPWR,
- VGND,
- VPB ,
- VNB
+ TE_B
);
output Z ;
input A ;
input TE_B;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/einvn/sky130_fd_sc_hdll__einvn_8.v b/cells/einvn/sky130_fd_sc_hdll__einvn_8.v
index 790a28a..1042874 100644
--- a/cells/einvn/sky130_fd_sc_hdll__einvn_8.v
+++ b/cells/einvn/sky130_fd_sc_hdll__einvn_8.v
@@ -74,20 +74,12 @@
module sky130_fd_sc_hdll__einvn_8 (
Z ,
A ,
- TE_B,
- VPWR,
- VGND,
- VPB ,
- VNB
+ TE_B
);
output Z ;
input A ;
input TE_B;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/einvp/sky130_fd_sc_hdll__einvp_1.v b/cells/einvp/sky130_fd_sc_hdll__einvp_1.v
index c2555ff..e1e5cdc 100644
--- a/cells/einvp/sky130_fd_sc_hdll__einvp_1.v
+++ b/cells/einvp/sky130_fd_sc_hdll__einvp_1.v
@@ -72,22 +72,14 @@
`celldefine
module sky130_fd_sc_hdll__einvp_1 (
- Z ,
- A ,
- TE ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Z ,
+ A ,
+ TE
);
- output Z ;
- input A ;
- input TE ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Z ;
+ input A ;
+ input TE;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/einvp/sky130_fd_sc_hdll__einvp_2.v b/cells/einvp/sky130_fd_sc_hdll__einvp_2.v
index c707a7d..fd0fabb 100644
--- a/cells/einvp/sky130_fd_sc_hdll__einvp_2.v
+++ b/cells/einvp/sky130_fd_sc_hdll__einvp_2.v
@@ -72,22 +72,14 @@
`celldefine
module sky130_fd_sc_hdll__einvp_2 (
- Z ,
- A ,
- TE ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Z ,
+ A ,
+ TE
);
- output Z ;
- input A ;
- input TE ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Z ;
+ input A ;
+ input TE;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/einvp/sky130_fd_sc_hdll__einvp_4.v b/cells/einvp/sky130_fd_sc_hdll__einvp_4.v
index b82e7aa..c46ef17 100644
--- a/cells/einvp/sky130_fd_sc_hdll__einvp_4.v
+++ b/cells/einvp/sky130_fd_sc_hdll__einvp_4.v
@@ -72,22 +72,14 @@
`celldefine
module sky130_fd_sc_hdll__einvp_4 (
- Z ,
- A ,
- TE ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Z ,
+ A ,
+ TE
);
- output Z ;
- input A ;
- input TE ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Z ;
+ input A ;
+ input TE;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/einvp/sky130_fd_sc_hdll__einvp_8.v b/cells/einvp/sky130_fd_sc_hdll__einvp_8.v
index 3afde24..e51e501 100644
--- a/cells/einvp/sky130_fd_sc_hdll__einvp_8.v
+++ b/cells/einvp/sky130_fd_sc_hdll__einvp_8.v
@@ -72,22 +72,14 @@
`celldefine
module sky130_fd_sc_hdll__einvp_8 (
- Z ,
- A ,
- TE ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Z ,
+ A ,
+ TE
);
- output Z ;
- input A ;
- input TE ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Z ;
+ input A ;
+ input TE;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/fill/sky130_fd_sc_hdll__fill_1.v b/cells/fill/sky130_fd_sc_hdll__fill_1.v
index 8bbeed3..9c059e3 100644
--- a/cells/fill/sky130_fd_sc_hdll__fill_1.v
+++ b/cells/fill/sky130_fd_sc_hdll__fill_1.v
@@ -62,18 +62,7 @@
/*********************************************************/
`celldefine
-module sky130_fd_sc_hdll__fill_1 (
- VPWR,
- VGND,
- VPB ,
- VNB
-);
-
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
-
+module sky130_fd_sc_hdll__fill_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
diff --git a/cells/fill/sky130_fd_sc_hdll__fill_2.v b/cells/fill/sky130_fd_sc_hdll__fill_2.v
index 7444cee..d46b9f5 100644
--- a/cells/fill/sky130_fd_sc_hdll__fill_2.v
+++ b/cells/fill/sky130_fd_sc_hdll__fill_2.v
@@ -62,18 +62,7 @@
/*********************************************************/
`celldefine
-module sky130_fd_sc_hdll__fill_2 (
- VPWR,
- VGND,
- VPB ,
- VNB
-);
-
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
-
+module sky130_fd_sc_hdll__fill_2 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
diff --git a/cells/fill/sky130_fd_sc_hdll__fill_4.v b/cells/fill/sky130_fd_sc_hdll__fill_4.v
index 7806822..710995b 100644
--- a/cells/fill/sky130_fd_sc_hdll__fill_4.v
+++ b/cells/fill/sky130_fd_sc_hdll__fill_4.v
@@ -62,18 +62,7 @@
/*********************************************************/
`celldefine
-module sky130_fd_sc_hdll__fill_4 (
- VPWR,
- VGND,
- VPB ,
- VNB
-);
-
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
-
+module sky130_fd_sc_hdll__fill_4 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
diff --git a/cells/fill/sky130_fd_sc_hdll__fill_8.v b/cells/fill/sky130_fd_sc_hdll__fill_8.v
index 160c025..823022b 100644
--- a/cells/fill/sky130_fd_sc_hdll__fill_8.v
+++ b/cells/fill/sky130_fd_sc_hdll__fill_8.v
@@ -62,18 +62,7 @@
/*********************************************************/
`celldefine
-module sky130_fd_sc_hdll__fill_8 (
- VPWR,
- VGND,
- VPB ,
- VNB
-);
-
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
-
+module sky130_fd_sc_hdll__fill_8 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
diff --git a/cells/inputiso0n/sky130_fd_sc_hdll__inputiso0n_1.v b/cells/inputiso0n/sky130_fd_sc_hdll__inputiso0n_1.v
index db63838..1a00276 100644
--- a/cells/inputiso0n/sky130_fd_sc_hdll__inputiso0n_1.v
+++ b/cells/inputiso0n/sky130_fd_sc_hdll__inputiso0n_1.v
@@ -76,20 +76,12 @@
module sky130_fd_sc_hdll__inputiso0n_1 (
X ,
A ,
- SLEEP_B,
- VPWR ,
- VGND ,
- VPB ,
- VNB
+ SLEEP_B
);
output X ;
input A ;
input SLEEP_B;
- input VPWR ;
- input VGND ;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/inputiso0p/sky130_fd_sc_hdll__inputiso0p_1.v b/cells/inputiso0p/sky130_fd_sc_hdll__inputiso0p_1.v
index b01b160..7392cae 100644
--- a/cells/inputiso0p/sky130_fd_sc_hdll__inputiso0p_1.v
+++ b/cells/inputiso0p/sky130_fd_sc_hdll__inputiso0p_1.v
@@ -76,20 +76,12 @@
module sky130_fd_sc_hdll__inputiso0p_1 (
X ,
A ,
- SLEEP,
- VPWR ,
- VGND ,
- VPB ,
- VNB
+ SLEEP
);
output X ;
input A ;
input SLEEP;
- input VPWR ;
- input VGND ;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/inputiso1n/sky130_fd_sc_hdll__inputiso1n_1.v b/cells/inputiso1n/sky130_fd_sc_hdll__inputiso1n_1.v
index 02d2c88..2e05bf9 100644
--- a/cells/inputiso1n/sky130_fd_sc_hdll__inputiso1n_1.v
+++ b/cells/inputiso1n/sky130_fd_sc_hdll__inputiso1n_1.v
@@ -76,20 +76,12 @@
module sky130_fd_sc_hdll__inputiso1n_1 (
X ,
A ,
- SLEEP_B,
- VPWR ,
- VGND ,
- VPB ,
- VNB
+ SLEEP_B
);
output X ;
input A ;
input SLEEP_B;
- input VPWR ;
- input VGND ;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/inputiso1p/sky130_fd_sc_hdll__inputiso1p_1.v b/cells/inputiso1p/sky130_fd_sc_hdll__inputiso1p_1.v
index 9132c5a..a15c7d2 100644
--- a/cells/inputiso1p/sky130_fd_sc_hdll__inputiso1p_1.v
+++ b/cells/inputiso1p/sky130_fd_sc_hdll__inputiso1p_1.v
@@ -76,20 +76,12 @@
module sky130_fd_sc_hdll__inputiso1p_1 (
X ,
A ,
- SLEEP,
- VPWR ,
- VGND ,
- VPB ,
- VNB
+ SLEEP
);
output X ;
input A ;
input SLEEP;
- input VPWR ;
- input VGND ;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/inv/sky130_fd_sc_hdll__inv_1.v b/cells/inv/sky130_fd_sc_hdll__inv_1.v
index 2990ff1..b5eb807 100644
--- a/cells/inv/sky130_fd_sc_hdll__inv_1.v
+++ b/cells/inv/sky130_fd_sc_hdll__inv_1.v
@@ -69,20 +69,12 @@
`celldefine
module sky130_fd_sc_hdll__inv_1 (
- Y ,
- A ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A
);
- output Y ;
- input A ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/inv/sky130_fd_sc_hdll__inv_12.v b/cells/inv/sky130_fd_sc_hdll__inv_12.v
index 740282b..b78ac1e 100644
--- a/cells/inv/sky130_fd_sc_hdll__inv_12.v
+++ b/cells/inv/sky130_fd_sc_hdll__inv_12.v
@@ -69,20 +69,12 @@
`celldefine
module sky130_fd_sc_hdll__inv_12 (
- Y ,
- A ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A
);
- output Y ;
- input A ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/inv/sky130_fd_sc_hdll__inv_16.v b/cells/inv/sky130_fd_sc_hdll__inv_16.v
index 5442b0b..f0ca08f 100644
--- a/cells/inv/sky130_fd_sc_hdll__inv_16.v
+++ b/cells/inv/sky130_fd_sc_hdll__inv_16.v
@@ -69,20 +69,12 @@
`celldefine
module sky130_fd_sc_hdll__inv_16 (
- Y ,
- A ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A
);
- output Y ;
- input A ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/inv/sky130_fd_sc_hdll__inv_2.v b/cells/inv/sky130_fd_sc_hdll__inv_2.v
index f721014..ef3f173 100644
--- a/cells/inv/sky130_fd_sc_hdll__inv_2.v
+++ b/cells/inv/sky130_fd_sc_hdll__inv_2.v
@@ -69,20 +69,12 @@
`celldefine
module sky130_fd_sc_hdll__inv_2 (
- Y ,
- A ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A
);
- output Y ;
- input A ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/inv/sky130_fd_sc_hdll__inv_4.v b/cells/inv/sky130_fd_sc_hdll__inv_4.v
index 17b5957..acff136 100644
--- a/cells/inv/sky130_fd_sc_hdll__inv_4.v
+++ b/cells/inv/sky130_fd_sc_hdll__inv_4.v
@@ -69,20 +69,12 @@
`celldefine
module sky130_fd_sc_hdll__inv_4 (
- Y ,
- A ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A
);
- output Y ;
- input A ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/inv/sky130_fd_sc_hdll__inv_6.v b/cells/inv/sky130_fd_sc_hdll__inv_6.v
index 5328b88..8529db0 100644
--- a/cells/inv/sky130_fd_sc_hdll__inv_6.v
+++ b/cells/inv/sky130_fd_sc_hdll__inv_6.v
@@ -69,20 +69,12 @@
`celldefine
module sky130_fd_sc_hdll__inv_6 (
- Y ,
- A ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A
);
- output Y ;
- input A ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/inv/sky130_fd_sc_hdll__inv_8.v b/cells/inv/sky130_fd_sc_hdll__inv_8.v
index e759c70..8ae9045 100644
--- a/cells/inv/sky130_fd_sc_hdll__inv_8.v
+++ b/cells/inv/sky130_fd_sc_hdll__inv_8.v
@@ -69,20 +69,12 @@
`celldefine
module sky130_fd_sc_hdll__inv_8 (
- Y ,
- A ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A
);
- output Y ;
- input A ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/isobufsrc/sky130_fd_sc_hdll__isobufsrc_1.v b/cells/isobufsrc/sky130_fd_sc_hdll__isobufsrc_1.v
index 9bbf492..e426c7e 100644
--- a/cells/isobufsrc/sky130_fd_sc_hdll__isobufsrc_1.v
+++ b/cells/isobufsrc/sky130_fd_sc_hdll__isobufsrc_1.v
@@ -76,20 +76,12 @@
module sky130_fd_sc_hdll__isobufsrc_1 (
X ,
SLEEP,
- A ,
- VPWR ,
- VGND ,
- VPB ,
- VNB
+ A
);
output X ;
input SLEEP;
input A ;
- input VPWR ;
- input VGND ;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/isobufsrc/sky130_fd_sc_hdll__isobufsrc_16.v b/cells/isobufsrc/sky130_fd_sc_hdll__isobufsrc_16.v
index 9c36b3a..57a9c6d 100644
--- a/cells/isobufsrc/sky130_fd_sc_hdll__isobufsrc_16.v
+++ b/cells/isobufsrc/sky130_fd_sc_hdll__isobufsrc_16.v
@@ -76,20 +76,12 @@
module sky130_fd_sc_hdll__isobufsrc_16 (
X ,
SLEEP,
- A ,
- VPWR ,
- VGND ,
- VPB ,
- VNB
+ A
);
output X ;
input SLEEP;
input A ;
- input VPWR ;
- input VGND ;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/isobufsrc/sky130_fd_sc_hdll__isobufsrc_2.v b/cells/isobufsrc/sky130_fd_sc_hdll__isobufsrc_2.v
index 470707a..362dfef 100644
--- a/cells/isobufsrc/sky130_fd_sc_hdll__isobufsrc_2.v
+++ b/cells/isobufsrc/sky130_fd_sc_hdll__isobufsrc_2.v
@@ -76,20 +76,12 @@
module sky130_fd_sc_hdll__isobufsrc_2 (
X ,
SLEEP,
- A ,
- VPWR ,
- VGND ,
- VPB ,
- VNB
+ A
);
output X ;
input SLEEP;
input A ;
- input VPWR ;
- input VGND ;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/isobufsrc/sky130_fd_sc_hdll__isobufsrc_4.v b/cells/isobufsrc/sky130_fd_sc_hdll__isobufsrc_4.v
index 7290168..43b4dad 100644
--- a/cells/isobufsrc/sky130_fd_sc_hdll__isobufsrc_4.v
+++ b/cells/isobufsrc/sky130_fd_sc_hdll__isobufsrc_4.v
@@ -76,20 +76,12 @@
module sky130_fd_sc_hdll__isobufsrc_4 (
X ,
SLEEP,
- A ,
- VPWR ,
- VGND ,
- VPB ,
- VNB
+ A
);
output X ;
input SLEEP;
input A ;
- input VPWR ;
- input VGND ;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/isobufsrc/sky130_fd_sc_hdll__isobufsrc_8.v b/cells/isobufsrc/sky130_fd_sc_hdll__isobufsrc_8.v
index 3805609..d253fc7 100644
--- a/cells/isobufsrc/sky130_fd_sc_hdll__isobufsrc_8.v
+++ b/cells/isobufsrc/sky130_fd_sc_hdll__isobufsrc_8.v
@@ -76,20 +76,12 @@
module sky130_fd_sc_hdll__isobufsrc_8 (
X ,
SLEEP,
- A ,
- VPWR ,
- VGND ,
- VPB ,
- VNB
+ A
);
output X ;
input SLEEP;
input A ;
- input VPWR ;
- input VGND ;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/mux2/sky130_fd_sc_hdll__mux2_1.v b/cells/mux2/sky130_fd_sc_hdll__mux2_1.v
index 2ce12ac..d249317 100644
--- a/cells/mux2/sky130_fd_sc_hdll__mux2_1.v
+++ b/cells/mux2/sky130_fd_sc_hdll__mux2_1.v
@@ -75,24 +75,16 @@
`celldefine
module sky130_fd_sc_hdll__mux2_1 (
- X ,
- A0 ,
- A1 ,
- S ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A0,
+ A1,
+ S
);
- output X ;
- input A0 ;
- input A1 ;
- input S ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A0;
+ input A1;
+ input S ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/mux2/sky130_fd_sc_hdll__mux2_12.v b/cells/mux2/sky130_fd_sc_hdll__mux2_12.v
index 852e47d..5f75edf 100644
--- a/cells/mux2/sky130_fd_sc_hdll__mux2_12.v
+++ b/cells/mux2/sky130_fd_sc_hdll__mux2_12.v
@@ -75,24 +75,16 @@
`celldefine
module sky130_fd_sc_hdll__mux2_12 (
- X ,
- A0 ,
- A1 ,
- S ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A0,
+ A1,
+ S
);
- output X ;
- input A0 ;
- input A1 ;
- input S ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A0;
+ input A1;
+ input S ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/mux2/sky130_fd_sc_hdll__mux2_16.v b/cells/mux2/sky130_fd_sc_hdll__mux2_16.v
index 27b13a6..fd92b63 100644
--- a/cells/mux2/sky130_fd_sc_hdll__mux2_16.v
+++ b/cells/mux2/sky130_fd_sc_hdll__mux2_16.v
@@ -75,24 +75,16 @@
`celldefine
module sky130_fd_sc_hdll__mux2_16 (
- X ,
- A0 ,
- A1 ,
- S ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A0,
+ A1,
+ S
);
- output X ;
- input A0 ;
- input A1 ;
- input S ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A0;
+ input A1;
+ input S ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/mux2/sky130_fd_sc_hdll__mux2_2.v b/cells/mux2/sky130_fd_sc_hdll__mux2_2.v
index f68e1e8..763ecdd 100644
--- a/cells/mux2/sky130_fd_sc_hdll__mux2_2.v
+++ b/cells/mux2/sky130_fd_sc_hdll__mux2_2.v
@@ -75,24 +75,16 @@
`celldefine
module sky130_fd_sc_hdll__mux2_2 (
- X ,
- A0 ,
- A1 ,
- S ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A0,
+ A1,
+ S
);
- output X ;
- input A0 ;
- input A1 ;
- input S ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A0;
+ input A1;
+ input S ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/mux2/sky130_fd_sc_hdll__mux2_4.v b/cells/mux2/sky130_fd_sc_hdll__mux2_4.v
index 2c08a55..2a66e74 100644
--- a/cells/mux2/sky130_fd_sc_hdll__mux2_4.v
+++ b/cells/mux2/sky130_fd_sc_hdll__mux2_4.v
@@ -75,24 +75,16 @@
`celldefine
module sky130_fd_sc_hdll__mux2_4 (
- X ,
- A0 ,
- A1 ,
- S ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A0,
+ A1,
+ S
);
- output X ;
- input A0 ;
- input A1 ;
- input S ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A0;
+ input A1;
+ input S ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/mux2/sky130_fd_sc_hdll__mux2_8.v b/cells/mux2/sky130_fd_sc_hdll__mux2_8.v
index 69aaa1a..9ff159e 100644
--- a/cells/mux2/sky130_fd_sc_hdll__mux2_8.v
+++ b/cells/mux2/sky130_fd_sc_hdll__mux2_8.v
@@ -75,24 +75,16 @@
`celldefine
module sky130_fd_sc_hdll__mux2_8 (
- X ,
- A0 ,
- A1 ,
- S ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A0,
+ A1,
+ S
);
- output X ;
- input A0 ;
- input A1 ;
- input S ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A0;
+ input A1;
+ input S ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/mux2i/sky130_fd_sc_hdll__mux2i_1.v b/cells/mux2i/sky130_fd_sc_hdll__mux2i_1.v
index b8daa7e..e88ed34 100644
--- a/cells/mux2i/sky130_fd_sc_hdll__mux2i_1.v
+++ b/cells/mux2i/sky130_fd_sc_hdll__mux2i_1.v
@@ -75,24 +75,16 @@
`celldefine
module sky130_fd_sc_hdll__mux2i_1 (
- Y ,
- A0 ,
- A1 ,
- S ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A0,
+ A1,
+ S
);
- output Y ;
- input A0 ;
- input A1 ;
- input S ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A0;
+ input A1;
+ input S ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/mux2i/sky130_fd_sc_hdll__mux2i_2.v b/cells/mux2i/sky130_fd_sc_hdll__mux2i_2.v
index 608bb25..283257e 100644
--- a/cells/mux2i/sky130_fd_sc_hdll__mux2i_2.v
+++ b/cells/mux2i/sky130_fd_sc_hdll__mux2i_2.v
@@ -75,24 +75,16 @@
`celldefine
module sky130_fd_sc_hdll__mux2i_2 (
- Y ,
- A0 ,
- A1 ,
- S ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A0,
+ A1,
+ S
);
- output Y ;
- input A0 ;
- input A1 ;
- input S ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A0;
+ input A1;
+ input S ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/mux2i/sky130_fd_sc_hdll__mux2i_4.v b/cells/mux2i/sky130_fd_sc_hdll__mux2i_4.v
index 3ba6292..9edb67f 100644
--- a/cells/mux2i/sky130_fd_sc_hdll__mux2i_4.v
+++ b/cells/mux2i/sky130_fd_sc_hdll__mux2i_4.v
@@ -75,24 +75,16 @@
`celldefine
module sky130_fd_sc_hdll__mux2i_4 (
- Y ,
- A0 ,
- A1 ,
- S ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A0,
+ A1,
+ S
);
- output Y ;
- input A0 ;
- input A1 ;
- input S ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A0;
+ input A1;
+ input S ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/muxb16to1/sky130_fd_sc_hdll__muxb16to1_1.v b/cells/muxb16to1/sky130_fd_sc_hdll__muxb16to1_1.v
index 1389587..e1404e3 100644
--- a/cells/muxb16to1/sky130_fd_sc_hdll__muxb16to1_1.v
+++ b/cells/muxb16to1/sky130_fd_sc_hdll__muxb16to1_1.v
@@ -72,22 +72,14 @@
`celldefine
module sky130_fd_sc_hdll__muxb16to1_1 (
- Z ,
- D ,
- S ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Z,
+ D,
+ S
);
- output Z ;
- input [15:0] D ;
- input [15:0] S ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Z;
+ input [15:0] D;
+ input [15:0] S;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/muxb16to1/sky130_fd_sc_hdll__muxb16to1_2.v b/cells/muxb16to1/sky130_fd_sc_hdll__muxb16to1_2.v
index 1f0e0dd..d35226f 100644
--- a/cells/muxb16to1/sky130_fd_sc_hdll__muxb16to1_2.v
+++ b/cells/muxb16to1/sky130_fd_sc_hdll__muxb16to1_2.v
@@ -72,22 +72,14 @@
`celldefine
module sky130_fd_sc_hdll__muxb16to1_2 (
- Z ,
- D ,
- S ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Z,
+ D,
+ S
);
- output Z ;
- input [15:0] D ;
- input [15:0] S ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Z;
+ input [15:0] D;
+ input [15:0] S;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/muxb16to1/sky130_fd_sc_hdll__muxb16to1_4.v b/cells/muxb16to1/sky130_fd_sc_hdll__muxb16to1_4.v
index fe0ff17..3e53671 100644
--- a/cells/muxb16to1/sky130_fd_sc_hdll__muxb16to1_4.v
+++ b/cells/muxb16to1/sky130_fd_sc_hdll__muxb16to1_4.v
@@ -72,22 +72,14 @@
`celldefine
module sky130_fd_sc_hdll__muxb16to1_4 (
- Z ,
- D ,
- S ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Z,
+ D,
+ S
);
- output Z ;
- input [15:0] D ;
- input [15:0] S ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Z;
+ input [15:0] D;
+ input [15:0] S;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/muxb4to1/sky130_fd_sc_hdll__muxb4to1_1.v b/cells/muxb4to1/sky130_fd_sc_hdll__muxb4to1_1.v
index ce370b8..190d618 100644
--- a/cells/muxb4to1/sky130_fd_sc_hdll__muxb4to1_1.v
+++ b/cells/muxb4to1/sky130_fd_sc_hdll__muxb4to1_1.v
@@ -72,22 +72,14 @@
`celldefine
module sky130_fd_sc_hdll__muxb4to1_1 (
- Z ,
- D ,
- S ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Z,
+ D,
+ S
);
- output Z ;
- input [3:0] D ;
- input [3:0] S ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Z;
+ input [3:0] D;
+ input [3:0] S;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/muxb4to1/sky130_fd_sc_hdll__muxb4to1_2.v b/cells/muxb4to1/sky130_fd_sc_hdll__muxb4to1_2.v
index 51a56ea..3952b2e 100644
--- a/cells/muxb4to1/sky130_fd_sc_hdll__muxb4to1_2.v
+++ b/cells/muxb4to1/sky130_fd_sc_hdll__muxb4to1_2.v
@@ -72,22 +72,14 @@
`celldefine
module sky130_fd_sc_hdll__muxb4to1_2 (
- Z ,
- D ,
- S ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Z,
+ D,
+ S
);
- output Z ;
- input [3:0] D ;
- input [3:0] S ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Z;
+ input [3:0] D;
+ input [3:0] S;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/muxb4to1/sky130_fd_sc_hdll__muxb4to1_4.v b/cells/muxb4to1/sky130_fd_sc_hdll__muxb4to1_4.v
index b312d1e..0d3a7ee 100644
--- a/cells/muxb4to1/sky130_fd_sc_hdll__muxb4to1_4.v
+++ b/cells/muxb4to1/sky130_fd_sc_hdll__muxb4to1_4.v
@@ -72,22 +72,14 @@
`celldefine
module sky130_fd_sc_hdll__muxb4to1_4 (
- Z ,
- D ,
- S ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Z,
+ D,
+ S
);
- output Z ;
- input [3:0] D ;
- input [3:0] S ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Z;
+ input [3:0] D;
+ input [3:0] S;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/muxb8to1/sky130_fd_sc_hdll__muxb8to1_1.v b/cells/muxb8to1/sky130_fd_sc_hdll__muxb8to1_1.v
index 47d036c..c6f14a2 100644
--- a/cells/muxb8to1/sky130_fd_sc_hdll__muxb8to1_1.v
+++ b/cells/muxb8to1/sky130_fd_sc_hdll__muxb8to1_1.v
@@ -72,22 +72,14 @@
`celldefine
module sky130_fd_sc_hdll__muxb8to1_1 (
- Z ,
- D ,
- S ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Z,
+ D,
+ S
);
- output Z ;
- input [7:0] D ;
- input [7:0] S ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Z;
+ input [7:0] D;
+ input [7:0] S;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/muxb8to1/sky130_fd_sc_hdll__muxb8to1_2.v b/cells/muxb8to1/sky130_fd_sc_hdll__muxb8to1_2.v
index 5502363..26dd7c8 100644
--- a/cells/muxb8to1/sky130_fd_sc_hdll__muxb8to1_2.v
+++ b/cells/muxb8to1/sky130_fd_sc_hdll__muxb8to1_2.v
@@ -72,22 +72,14 @@
`celldefine
module sky130_fd_sc_hdll__muxb8to1_2 (
- Z ,
- D ,
- S ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Z,
+ D,
+ S
);
- output Z ;
- input [7:0] D ;
- input [7:0] S ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Z;
+ input [7:0] D;
+ input [7:0] S;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/muxb8to1/sky130_fd_sc_hdll__muxb8to1_4.v b/cells/muxb8to1/sky130_fd_sc_hdll__muxb8to1_4.v
index 9ecac57..b5119a4 100644
--- a/cells/muxb8to1/sky130_fd_sc_hdll__muxb8to1_4.v
+++ b/cells/muxb8to1/sky130_fd_sc_hdll__muxb8to1_4.v
@@ -72,22 +72,14 @@
`celldefine
module sky130_fd_sc_hdll__muxb8to1_4 (
- Z ,
- D ,
- S ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Z,
+ D,
+ S
);
- output Z ;
- input [7:0] D ;
- input [7:0] S ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Z;
+ input [7:0] D;
+ input [7:0] S;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/nand2/sky130_fd_sc_hdll__nand2_1.v b/cells/nand2/sky130_fd_sc_hdll__nand2_1.v
index 0813919..f866832 100644
--- a/cells/nand2/sky130_fd_sc_hdll__nand2_1.v
+++ b/cells/nand2/sky130_fd_sc_hdll__nand2_1.v
@@ -72,22 +72,14 @@
`celldefine
module sky130_fd_sc_hdll__nand2_1 (
- Y ,
- A ,
- B ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A,
+ B
);
- output Y ;
- input A ;
- input B ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
+ input B;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/nand2/sky130_fd_sc_hdll__nand2_12.v b/cells/nand2/sky130_fd_sc_hdll__nand2_12.v
index 00fabd8..307d1f6 100644
--- a/cells/nand2/sky130_fd_sc_hdll__nand2_12.v
+++ b/cells/nand2/sky130_fd_sc_hdll__nand2_12.v
@@ -72,22 +72,14 @@
`celldefine
module sky130_fd_sc_hdll__nand2_12 (
- Y ,
- A ,
- B ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A,
+ B
);
- output Y ;
- input A ;
- input B ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
+ input B;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/nand2/sky130_fd_sc_hdll__nand2_16.v b/cells/nand2/sky130_fd_sc_hdll__nand2_16.v
index 0f5fe99..b290ae4 100644
--- a/cells/nand2/sky130_fd_sc_hdll__nand2_16.v
+++ b/cells/nand2/sky130_fd_sc_hdll__nand2_16.v
@@ -72,22 +72,14 @@
`celldefine
module sky130_fd_sc_hdll__nand2_16 (
- Y ,
- A ,
- B ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A,
+ B
);
- output Y ;
- input A ;
- input B ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
+ input B;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/nand2/sky130_fd_sc_hdll__nand2_2.v b/cells/nand2/sky130_fd_sc_hdll__nand2_2.v
index f4b25c3..721f32c 100644
--- a/cells/nand2/sky130_fd_sc_hdll__nand2_2.v
+++ b/cells/nand2/sky130_fd_sc_hdll__nand2_2.v
@@ -72,22 +72,14 @@
`celldefine
module sky130_fd_sc_hdll__nand2_2 (
- Y ,
- A ,
- B ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A,
+ B
);
- output Y ;
- input A ;
- input B ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
+ input B;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/nand2/sky130_fd_sc_hdll__nand2_4.v b/cells/nand2/sky130_fd_sc_hdll__nand2_4.v
index 52accad..48e26a5 100644
--- a/cells/nand2/sky130_fd_sc_hdll__nand2_4.v
+++ b/cells/nand2/sky130_fd_sc_hdll__nand2_4.v
@@ -72,22 +72,14 @@
`celldefine
module sky130_fd_sc_hdll__nand2_4 (
- Y ,
- A ,
- B ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A,
+ B
);
- output Y ;
- input A ;
- input B ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
+ input B;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/nand2/sky130_fd_sc_hdll__nand2_6.v b/cells/nand2/sky130_fd_sc_hdll__nand2_6.v
index c4f2d46..87b23db 100644
--- a/cells/nand2/sky130_fd_sc_hdll__nand2_6.v
+++ b/cells/nand2/sky130_fd_sc_hdll__nand2_6.v
@@ -72,22 +72,14 @@
`celldefine
module sky130_fd_sc_hdll__nand2_6 (
- Y ,
- A ,
- B ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A,
+ B
);
- output Y ;
- input A ;
- input B ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
+ input B;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/nand2/sky130_fd_sc_hdll__nand2_8.v b/cells/nand2/sky130_fd_sc_hdll__nand2_8.v
index 17a6260..fff0135 100644
--- a/cells/nand2/sky130_fd_sc_hdll__nand2_8.v
+++ b/cells/nand2/sky130_fd_sc_hdll__nand2_8.v
@@ -72,22 +72,14 @@
`celldefine
module sky130_fd_sc_hdll__nand2_8 (
- Y ,
- A ,
- B ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A,
+ B
);
- output Y ;
- input A ;
- input B ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
+ input B;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/nand2b/sky130_fd_sc_hdll__nand2b_1.v b/cells/nand2b/sky130_fd_sc_hdll__nand2b_1.v
index c89ae93..d190c3e 100644
--- a/cells/nand2b/sky130_fd_sc_hdll__nand2b_1.v
+++ b/cells/nand2b/sky130_fd_sc_hdll__nand2b_1.v
@@ -72,22 +72,14 @@
`celldefine
module sky130_fd_sc_hdll__nand2b_1 (
- Y ,
- A_N ,
- B ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A_N,
+ B
);
- output Y ;
- input A_N ;
- input B ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A_N;
+ input B ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/nand2b/sky130_fd_sc_hdll__nand2b_2.v b/cells/nand2b/sky130_fd_sc_hdll__nand2b_2.v
index 7f88cf6..545ca03 100644
--- a/cells/nand2b/sky130_fd_sc_hdll__nand2b_2.v
+++ b/cells/nand2b/sky130_fd_sc_hdll__nand2b_2.v
@@ -72,22 +72,14 @@
`celldefine
module sky130_fd_sc_hdll__nand2b_2 (
- Y ,
- A_N ,
- B ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A_N,
+ B
);
- output Y ;
- input A_N ;
- input B ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A_N;
+ input B ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/nand2b/sky130_fd_sc_hdll__nand2b_4.v b/cells/nand2b/sky130_fd_sc_hdll__nand2b_4.v
index 3257cd3..9fb9859 100644
--- a/cells/nand2b/sky130_fd_sc_hdll__nand2b_4.v
+++ b/cells/nand2b/sky130_fd_sc_hdll__nand2b_4.v
@@ -72,22 +72,14 @@
`celldefine
module sky130_fd_sc_hdll__nand2b_4 (
- Y ,
- A_N ,
- B ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A_N,
+ B
);
- output Y ;
- input A_N ;
- input B ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A_N;
+ input B ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/nand3/sky130_fd_sc_hdll__nand3_1.v b/cells/nand3/sky130_fd_sc_hdll__nand3_1.v
index ea1d61c..128597d 100644
--- a/cells/nand3/sky130_fd_sc_hdll__nand3_1.v
+++ b/cells/nand3/sky130_fd_sc_hdll__nand3_1.v
@@ -75,24 +75,16 @@
`celldefine
module sky130_fd_sc_hdll__nand3_1 (
- Y ,
- A ,
- B ,
- C ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A,
+ B,
+ C
);
- output Y ;
- input A ;
- input B ;
- input C ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
+ input B;
+ input C;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/nand3/sky130_fd_sc_hdll__nand3_2.v b/cells/nand3/sky130_fd_sc_hdll__nand3_2.v
index 8795b15..0eb8794 100644
--- a/cells/nand3/sky130_fd_sc_hdll__nand3_2.v
+++ b/cells/nand3/sky130_fd_sc_hdll__nand3_2.v
@@ -75,24 +75,16 @@
`celldefine
module sky130_fd_sc_hdll__nand3_2 (
- Y ,
- A ,
- B ,
- C ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A,
+ B,
+ C
);
- output Y ;
- input A ;
- input B ;
- input C ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
+ input B;
+ input C;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/nand3/sky130_fd_sc_hdll__nand3_4.v b/cells/nand3/sky130_fd_sc_hdll__nand3_4.v
index 9fb89a6..b361895 100644
--- a/cells/nand3/sky130_fd_sc_hdll__nand3_4.v
+++ b/cells/nand3/sky130_fd_sc_hdll__nand3_4.v
@@ -75,24 +75,16 @@
`celldefine
module sky130_fd_sc_hdll__nand3_4 (
- Y ,
- A ,
- B ,
- C ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A,
+ B,
+ C
);
- output Y ;
- input A ;
- input B ;
- input C ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
+ input B;
+ input C;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/nand3b/sky130_fd_sc_hdll__nand3b_1.v b/cells/nand3b/sky130_fd_sc_hdll__nand3b_1.v
index 09bf755..0c9f600 100644
--- a/cells/nand3b/sky130_fd_sc_hdll__nand3b_1.v
+++ b/cells/nand3b/sky130_fd_sc_hdll__nand3b_1.v
@@ -75,24 +75,16 @@
`celldefine
module sky130_fd_sc_hdll__nand3b_1 (
- Y ,
- A_N ,
- B ,
- C ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A_N,
+ B ,
+ C
);
- output Y ;
- input A_N ;
- input B ;
- input C ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A_N;
+ input B ;
+ input C ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/nand3b/sky130_fd_sc_hdll__nand3b_2.v b/cells/nand3b/sky130_fd_sc_hdll__nand3b_2.v
index d2d8834..23a1d25 100644
--- a/cells/nand3b/sky130_fd_sc_hdll__nand3b_2.v
+++ b/cells/nand3b/sky130_fd_sc_hdll__nand3b_2.v
@@ -75,24 +75,16 @@
`celldefine
module sky130_fd_sc_hdll__nand3b_2 (
- Y ,
- A_N ,
- B ,
- C ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A_N,
+ B ,
+ C
);
- output Y ;
- input A_N ;
- input B ;
- input C ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A_N;
+ input B ;
+ input C ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/nand3b/sky130_fd_sc_hdll__nand3b_4.v b/cells/nand3b/sky130_fd_sc_hdll__nand3b_4.v
index d130405..da7d8a7 100644
--- a/cells/nand3b/sky130_fd_sc_hdll__nand3b_4.v
+++ b/cells/nand3b/sky130_fd_sc_hdll__nand3b_4.v
@@ -75,24 +75,16 @@
`celldefine
module sky130_fd_sc_hdll__nand3b_4 (
- Y ,
- A_N ,
- B ,
- C ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A_N,
+ B ,
+ C
);
- output Y ;
- input A_N ;
- input B ;
- input C ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A_N;
+ input B ;
+ input C ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/nand4/sky130_fd_sc_hdll__nand4_1.v b/cells/nand4/sky130_fd_sc_hdll__nand4_1.v
index d41c910..21da58e 100644
--- a/cells/nand4/sky130_fd_sc_hdll__nand4_1.v
+++ b/cells/nand4/sky130_fd_sc_hdll__nand4_1.v
@@ -78,26 +78,18 @@
`celldefine
module sky130_fd_sc_hdll__nand4_1 (
- Y ,
- A ,
- B ,
- C ,
- D ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A,
+ B,
+ C,
+ D
);
- output Y ;
- input A ;
- input B ;
- input C ;
- input D ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
+ input B;
+ input C;
+ input D;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/nand4/sky130_fd_sc_hdll__nand4_2.v b/cells/nand4/sky130_fd_sc_hdll__nand4_2.v
index 510b92d..e3f9b2a 100644
--- a/cells/nand4/sky130_fd_sc_hdll__nand4_2.v
+++ b/cells/nand4/sky130_fd_sc_hdll__nand4_2.v
@@ -78,26 +78,18 @@
`celldefine
module sky130_fd_sc_hdll__nand4_2 (
- Y ,
- A ,
- B ,
- C ,
- D ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A,
+ B,
+ C,
+ D
);
- output Y ;
- input A ;
- input B ;
- input C ;
- input D ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
+ input B;
+ input C;
+ input D;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/nand4/sky130_fd_sc_hdll__nand4_4.v b/cells/nand4/sky130_fd_sc_hdll__nand4_4.v
index f9f8725..ba5a62d 100644
--- a/cells/nand4/sky130_fd_sc_hdll__nand4_4.v
+++ b/cells/nand4/sky130_fd_sc_hdll__nand4_4.v
@@ -78,26 +78,18 @@
`celldefine
module sky130_fd_sc_hdll__nand4_4 (
- Y ,
- A ,
- B ,
- C ,
- D ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A,
+ B,
+ C,
+ D
);
- output Y ;
- input A ;
- input B ;
- input C ;
- input D ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
+ input B;
+ input C;
+ input D;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/nand4b/sky130_fd_sc_hdll__nand4b_1.v b/cells/nand4b/sky130_fd_sc_hdll__nand4b_1.v
index 5a1573d..db41f02 100644
--- a/cells/nand4b/sky130_fd_sc_hdll__nand4b_1.v
+++ b/cells/nand4b/sky130_fd_sc_hdll__nand4b_1.v
@@ -78,26 +78,18 @@
`celldefine
module sky130_fd_sc_hdll__nand4b_1 (
- Y ,
- A_N ,
- B ,
- C ,
- D ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A_N,
+ B ,
+ C ,
+ D
);
- output Y ;
- input A_N ;
- input B ;
- input C ;
- input D ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A_N;
+ input B ;
+ input C ;
+ input D ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/nand4b/sky130_fd_sc_hdll__nand4b_2.v b/cells/nand4b/sky130_fd_sc_hdll__nand4b_2.v
index 223da97..0c2ddaa 100644
--- a/cells/nand4b/sky130_fd_sc_hdll__nand4b_2.v
+++ b/cells/nand4b/sky130_fd_sc_hdll__nand4b_2.v
@@ -78,26 +78,18 @@
`celldefine
module sky130_fd_sc_hdll__nand4b_2 (
- Y ,
- A_N ,
- B ,
- C ,
- D ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A_N,
+ B ,
+ C ,
+ D
);
- output Y ;
- input A_N ;
- input B ;
- input C ;
- input D ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A_N;
+ input B ;
+ input C ;
+ input D ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/nand4b/sky130_fd_sc_hdll__nand4b_4.v b/cells/nand4b/sky130_fd_sc_hdll__nand4b_4.v
index 20310fc..3af631c 100644
--- a/cells/nand4b/sky130_fd_sc_hdll__nand4b_4.v
+++ b/cells/nand4b/sky130_fd_sc_hdll__nand4b_4.v
@@ -78,26 +78,18 @@
`celldefine
module sky130_fd_sc_hdll__nand4b_4 (
- Y ,
- A_N ,
- B ,
- C ,
- D ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A_N,
+ B ,
+ C ,
+ D
);
- output Y ;
- input A_N ;
- input B ;
- input C ;
- input D ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A_N;
+ input B ;
+ input C ;
+ input D ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/nand4bb/sky130_fd_sc_hdll__nand4bb_1.v b/cells/nand4bb/sky130_fd_sc_hdll__nand4bb_1.v
index 6bf857a..649fe06 100644
--- a/cells/nand4bb/sky130_fd_sc_hdll__nand4bb_1.v
+++ b/cells/nand4bb/sky130_fd_sc_hdll__nand4bb_1.v
@@ -78,26 +78,18 @@
`celldefine
module sky130_fd_sc_hdll__nand4bb_1 (
- Y ,
- A_N ,
- B_N ,
- C ,
- D ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A_N,
+ B_N,
+ C ,
+ D
);
- output Y ;
- input A_N ;
- input B_N ;
- input C ;
- input D ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A_N;
+ input B_N;
+ input C ;
+ input D ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/nand4bb/sky130_fd_sc_hdll__nand4bb_2.v b/cells/nand4bb/sky130_fd_sc_hdll__nand4bb_2.v
index ec37cd2..2c501d0 100644
--- a/cells/nand4bb/sky130_fd_sc_hdll__nand4bb_2.v
+++ b/cells/nand4bb/sky130_fd_sc_hdll__nand4bb_2.v
@@ -78,26 +78,18 @@
`celldefine
module sky130_fd_sc_hdll__nand4bb_2 (
- Y ,
- A_N ,
- B_N ,
- C ,
- D ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A_N,
+ B_N,
+ C ,
+ D
);
- output Y ;
- input A_N ;
- input B_N ;
- input C ;
- input D ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A_N;
+ input B_N;
+ input C ;
+ input D ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/nand4bb/sky130_fd_sc_hdll__nand4bb_4.v b/cells/nand4bb/sky130_fd_sc_hdll__nand4bb_4.v
index ce53eac..37e21d2 100644
--- a/cells/nand4bb/sky130_fd_sc_hdll__nand4bb_4.v
+++ b/cells/nand4bb/sky130_fd_sc_hdll__nand4bb_4.v
@@ -78,26 +78,18 @@
`celldefine
module sky130_fd_sc_hdll__nand4bb_4 (
- Y ,
- A_N ,
- B_N ,
- C ,
- D ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A_N,
+ B_N,
+ C ,
+ D
);
- output Y ;
- input A_N ;
- input B_N ;
- input C ;
- input D ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A_N;
+ input B_N;
+ input C ;
+ input D ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/nor2/sky130_fd_sc_hdll__nor2_1.v b/cells/nor2/sky130_fd_sc_hdll__nor2_1.v
index 9ac0fdc..00099e6 100644
--- a/cells/nor2/sky130_fd_sc_hdll__nor2_1.v
+++ b/cells/nor2/sky130_fd_sc_hdll__nor2_1.v
@@ -72,22 +72,14 @@
`celldefine
module sky130_fd_sc_hdll__nor2_1 (
- Y ,
- A ,
- B ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A,
+ B
);
- output Y ;
- input A ;
- input B ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
+ input B;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/nor2/sky130_fd_sc_hdll__nor2_2.v b/cells/nor2/sky130_fd_sc_hdll__nor2_2.v
index 0a20af2..9d40204 100644
--- a/cells/nor2/sky130_fd_sc_hdll__nor2_2.v
+++ b/cells/nor2/sky130_fd_sc_hdll__nor2_2.v
@@ -72,22 +72,14 @@
`celldefine
module sky130_fd_sc_hdll__nor2_2 (
- Y ,
- A ,
- B ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A,
+ B
);
- output Y ;
- input A ;
- input B ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
+ input B;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/nor2/sky130_fd_sc_hdll__nor2_4.v b/cells/nor2/sky130_fd_sc_hdll__nor2_4.v
index fdc6900..56ce4c7 100644
--- a/cells/nor2/sky130_fd_sc_hdll__nor2_4.v
+++ b/cells/nor2/sky130_fd_sc_hdll__nor2_4.v
@@ -72,22 +72,14 @@
`celldefine
module sky130_fd_sc_hdll__nor2_4 (
- Y ,
- A ,
- B ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A,
+ B
);
- output Y ;
- input A ;
- input B ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
+ input B;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/nor2/sky130_fd_sc_hdll__nor2_8.v b/cells/nor2/sky130_fd_sc_hdll__nor2_8.v
index 6cfe636..e0fc14c 100644
--- a/cells/nor2/sky130_fd_sc_hdll__nor2_8.v
+++ b/cells/nor2/sky130_fd_sc_hdll__nor2_8.v
@@ -72,22 +72,14 @@
`celldefine
module sky130_fd_sc_hdll__nor2_8 (
- Y ,
- A ,
- B ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A,
+ B
);
- output Y ;
- input A ;
- input B ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
+ input B;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/nor2b/sky130_fd_sc_hdll__nor2b_1.v b/cells/nor2b/sky130_fd_sc_hdll__nor2b_1.v
index aae5b06..5140d66 100644
--- a/cells/nor2b/sky130_fd_sc_hdll__nor2b_1.v
+++ b/cells/nor2b/sky130_fd_sc_hdll__nor2b_1.v
@@ -74,22 +74,14 @@
`celldefine
module sky130_fd_sc_hdll__nor2b_1 (
- Y ,
- A ,
- B_N ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A ,
+ B_N
);
- output Y ;
- input A ;
- input B_N ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A ;
+ input B_N;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/nor2b/sky130_fd_sc_hdll__nor2b_2.v b/cells/nor2b/sky130_fd_sc_hdll__nor2b_2.v
index a27e648..d4f8c8c 100644
--- a/cells/nor2b/sky130_fd_sc_hdll__nor2b_2.v
+++ b/cells/nor2b/sky130_fd_sc_hdll__nor2b_2.v
@@ -74,22 +74,14 @@
`celldefine
module sky130_fd_sc_hdll__nor2b_2 (
- Y ,
- A ,
- B_N ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A ,
+ B_N
);
- output Y ;
- input A ;
- input B_N ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A ;
+ input B_N;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/nor2b/sky130_fd_sc_hdll__nor2b_4.v b/cells/nor2b/sky130_fd_sc_hdll__nor2b_4.v
index 2fac587..6006ae6 100644
--- a/cells/nor2b/sky130_fd_sc_hdll__nor2b_4.v
+++ b/cells/nor2b/sky130_fd_sc_hdll__nor2b_4.v
@@ -74,22 +74,14 @@
`celldefine
module sky130_fd_sc_hdll__nor2b_4 (
- Y ,
- A ,
- B_N ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A ,
+ B_N
);
- output Y ;
- input A ;
- input B_N ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A ;
+ input B_N;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/nor3/sky130_fd_sc_hdll__nor3_1.v b/cells/nor3/sky130_fd_sc_hdll__nor3_1.v
index 4a6820f..4b85d39 100644
--- a/cells/nor3/sky130_fd_sc_hdll__nor3_1.v
+++ b/cells/nor3/sky130_fd_sc_hdll__nor3_1.v
@@ -77,24 +77,16 @@
`celldefine
module sky130_fd_sc_hdll__nor3_1 (
- Y ,
- A ,
- B ,
- C ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A,
+ B,
+ C
);
- output Y ;
- input A ;
- input B ;
- input C ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
+ input B;
+ input C;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/nor3/sky130_fd_sc_hdll__nor3_2.v b/cells/nor3/sky130_fd_sc_hdll__nor3_2.v
index 6555bfa..30a3ed3 100644
--- a/cells/nor3/sky130_fd_sc_hdll__nor3_2.v
+++ b/cells/nor3/sky130_fd_sc_hdll__nor3_2.v
@@ -77,24 +77,16 @@
`celldefine
module sky130_fd_sc_hdll__nor3_2 (
- Y ,
- A ,
- B ,
- C ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A,
+ B,
+ C
);
- output Y ;
- input A ;
- input B ;
- input C ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
+ input B;
+ input C;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/nor3/sky130_fd_sc_hdll__nor3_4.v b/cells/nor3/sky130_fd_sc_hdll__nor3_4.v
index ab0fd38..f738d7b 100644
--- a/cells/nor3/sky130_fd_sc_hdll__nor3_4.v
+++ b/cells/nor3/sky130_fd_sc_hdll__nor3_4.v
@@ -77,24 +77,16 @@
`celldefine
module sky130_fd_sc_hdll__nor3_4 (
- Y ,
- A ,
- B ,
- C ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A,
+ B,
+ C
);
- output Y ;
- input A ;
- input B ;
- input C ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
+ input B;
+ input C;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/nor3b/sky130_fd_sc_hdll__nor3b_1.v b/cells/nor3b/sky130_fd_sc_hdll__nor3b_1.v
index b8872e6..16d2884 100644
--- a/cells/nor3b/sky130_fd_sc_hdll__nor3b_1.v
+++ b/cells/nor3b/sky130_fd_sc_hdll__nor3b_1.v
@@ -77,24 +77,16 @@
`celldefine
module sky130_fd_sc_hdll__nor3b_1 (
- Y ,
- A ,
- B ,
- C_N ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A ,
+ B ,
+ C_N
);
- output Y ;
- input A ;
- input B ;
- input C_N ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A ;
+ input B ;
+ input C_N;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/nor3b/sky130_fd_sc_hdll__nor3b_2.v b/cells/nor3b/sky130_fd_sc_hdll__nor3b_2.v
index 7932a0c..4067560 100644
--- a/cells/nor3b/sky130_fd_sc_hdll__nor3b_2.v
+++ b/cells/nor3b/sky130_fd_sc_hdll__nor3b_2.v
@@ -77,24 +77,16 @@
`celldefine
module sky130_fd_sc_hdll__nor3b_2 (
- Y ,
- A ,
- B ,
- C_N ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A ,
+ B ,
+ C_N
);
- output Y ;
- input A ;
- input B ;
- input C_N ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A ;
+ input B ;
+ input C_N;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/nor3b/sky130_fd_sc_hdll__nor3b_4.v b/cells/nor3b/sky130_fd_sc_hdll__nor3b_4.v
index cc673b7..2459dfc 100644
--- a/cells/nor3b/sky130_fd_sc_hdll__nor3b_4.v
+++ b/cells/nor3b/sky130_fd_sc_hdll__nor3b_4.v
@@ -77,24 +77,16 @@
`celldefine
module sky130_fd_sc_hdll__nor3b_4 (
- Y ,
- A ,
- B ,
- C_N ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A ,
+ B ,
+ C_N
);
- output Y ;
- input A ;
- input B ;
- input C_N ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A ;
+ input B ;
+ input C_N;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/nor4/sky130_fd_sc_hdll__nor4_1.v b/cells/nor4/sky130_fd_sc_hdll__nor4_1.v
index d9340ce..ff45464 100644
--- a/cells/nor4/sky130_fd_sc_hdll__nor4_1.v
+++ b/cells/nor4/sky130_fd_sc_hdll__nor4_1.v
@@ -80,26 +80,18 @@
`celldefine
module sky130_fd_sc_hdll__nor4_1 (
- Y ,
- A ,
- B ,
- C ,
- D ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A,
+ B,
+ C,
+ D
);
- output Y ;
- input A ;
- input B ;
- input C ;
- input D ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
+ input B;
+ input C;
+ input D;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/nor4/sky130_fd_sc_hdll__nor4_2.v b/cells/nor4/sky130_fd_sc_hdll__nor4_2.v
index a358c58..0f59c62 100644
--- a/cells/nor4/sky130_fd_sc_hdll__nor4_2.v
+++ b/cells/nor4/sky130_fd_sc_hdll__nor4_2.v
@@ -80,26 +80,18 @@
`celldefine
module sky130_fd_sc_hdll__nor4_2 (
- Y ,
- A ,
- B ,
- C ,
- D ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A,
+ B,
+ C,
+ D
);
- output Y ;
- input A ;
- input B ;
- input C ;
- input D ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
+ input B;
+ input C;
+ input D;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/nor4/sky130_fd_sc_hdll__nor4_4.v b/cells/nor4/sky130_fd_sc_hdll__nor4_4.v
index 4516b46..2c75093 100644
--- a/cells/nor4/sky130_fd_sc_hdll__nor4_4.v
+++ b/cells/nor4/sky130_fd_sc_hdll__nor4_4.v
@@ -80,26 +80,18 @@
`celldefine
module sky130_fd_sc_hdll__nor4_4 (
- Y ,
- A ,
- B ,
- C ,
- D ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A,
+ B,
+ C,
+ D
);
- output Y ;
- input A ;
- input B ;
- input C ;
- input D ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
+ input B;
+ input C;
+ input D;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/nor4/sky130_fd_sc_hdll__nor4_6.v b/cells/nor4/sky130_fd_sc_hdll__nor4_6.v
index 5e206ed..c2cef53 100644
--- a/cells/nor4/sky130_fd_sc_hdll__nor4_6.v
+++ b/cells/nor4/sky130_fd_sc_hdll__nor4_6.v
@@ -80,26 +80,18 @@
`celldefine
module sky130_fd_sc_hdll__nor4_6 (
- Y ,
- A ,
- B ,
- C ,
- D ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A,
+ B,
+ C,
+ D
);
- output Y ;
- input A ;
- input B ;
- input C ;
- input D ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
+ input B;
+ input C;
+ input D;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/nor4/sky130_fd_sc_hdll__nor4_8.v b/cells/nor4/sky130_fd_sc_hdll__nor4_8.v
index be1dd3c..94db209 100644
--- a/cells/nor4/sky130_fd_sc_hdll__nor4_8.v
+++ b/cells/nor4/sky130_fd_sc_hdll__nor4_8.v
@@ -80,26 +80,18 @@
`celldefine
module sky130_fd_sc_hdll__nor4_8 (
- Y ,
- A ,
- B ,
- C ,
- D ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A,
+ B,
+ C,
+ D
);
- output Y ;
- input A ;
- input B ;
- input C ;
- input D ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
+ input B;
+ input C;
+ input D;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/nor4b/sky130_fd_sc_hdll__nor4b_1.v b/cells/nor4b/sky130_fd_sc_hdll__nor4b_1.v
index 34a8f2e..3dee5be 100644
--- a/cells/nor4b/sky130_fd_sc_hdll__nor4b_1.v
+++ b/cells/nor4b/sky130_fd_sc_hdll__nor4b_1.v
@@ -78,26 +78,18 @@
`celldefine
module sky130_fd_sc_hdll__nor4b_1 (
- Y ,
- A ,
- B ,
- C ,
- D_N ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A ,
+ B ,
+ C ,
+ D_N
);
- output Y ;
- input A ;
- input B ;
- input C ;
- input D_N ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A ;
+ input B ;
+ input C ;
+ input D_N;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/nor4b/sky130_fd_sc_hdll__nor4b_2.v b/cells/nor4b/sky130_fd_sc_hdll__nor4b_2.v
index 34021e5..aa93499 100644
--- a/cells/nor4b/sky130_fd_sc_hdll__nor4b_2.v
+++ b/cells/nor4b/sky130_fd_sc_hdll__nor4b_2.v
@@ -78,26 +78,18 @@
`celldefine
module sky130_fd_sc_hdll__nor4b_2 (
- Y ,
- A ,
- B ,
- C ,
- D_N ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A ,
+ B ,
+ C ,
+ D_N
);
- output Y ;
- input A ;
- input B ;
- input C ;
- input D_N ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A ;
+ input B ;
+ input C ;
+ input D_N;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/nor4b/sky130_fd_sc_hdll__nor4b_4.v b/cells/nor4b/sky130_fd_sc_hdll__nor4b_4.v
index f0addfa..93305f6 100644
--- a/cells/nor4b/sky130_fd_sc_hdll__nor4b_4.v
+++ b/cells/nor4b/sky130_fd_sc_hdll__nor4b_4.v
@@ -78,26 +78,18 @@
`celldefine
module sky130_fd_sc_hdll__nor4b_4 (
- Y ,
- A ,
- B ,
- C ,
- D_N ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A ,
+ B ,
+ C ,
+ D_N
);
- output Y ;
- input A ;
- input B ;
- input C ;
- input D_N ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A ;
+ input B ;
+ input C ;
+ input D_N;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/nor4bb/sky130_fd_sc_hdll__nor4bb_1.v b/cells/nor4bb/sky130_fd_sc_hdll__nor4bb_1.v
index fb92d12..e9414e6 100644
--- a/cells/nor4bb/sky130_fd_sc_hdll__nor4bb_1.v
+++ b/cells/nor4bb/sky130_fd_sc_hdll__nor4bb_1.v
@@ -78,26 +78,18 @@
`celldefine
module sky130_fd_sc_hdll__nor4bb_1 (
- Y ,
- A ,
- B ,
- C_N ,
- D_N ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A ,
+ B ,
+ C_N,
+ D_N
);
- output Y ;
- input A ;
- input B ;
- input C_N ;
- input D_N ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A ;
+ input B ;
+ input C_N;
+ input D_N;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/nor4bb/sky130_fd_sc_hdll__nor4bb_2.v b/cells/nor4bb/sky130_fd_sc_hdll__nor4bb_2.v
index f23a636..86e3b11 100644
--- a/cells/nor4bb/sky130_fd_sc_hdll__nor4bb_2.v
+++ b/cells/nor4bb/sky130_fd_sc_hdll__nor4bb_2.v
@@ -78,26 +78,18 @@
`celldefine
module sky130_fd_sc_hdll__nor4bb_2 (
- Y ,
- A ,
- B ,
- C_N ,
- D_N ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A ,
+ B ,
+ C_N,
+ D_N
);
- output Y ;
- input A ;
- input B ;
- input C_N ;
- input D_N ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A ;
+ input B ;
+ input C_N;
+ input D_N;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/nor4bb/sky130_fd_sc_hdll__nor4bb_4.v b/cells/nor4bb/sky130_fd_sc_hdll__nor4bb_4.v
index 4206303..928e1ad 100644
--- a/cells/nor4bb/sky130_fd_sc_hdll__nor4bb_4.v
+++ b/cells/nor4bb/sky130_fd_sc_hdll__nor4bb_4.v
@@ -78,26 +78,18 @@
`celldefine
module sky130_fd_sc_hdll__nor4bb_4 (
- Y ,
- A ,
- B ,
- C_N ,
- D_N ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A ,
+ B ,
+ C_N,
+ D_N
);
- output Y ;
- input A ;
- input B ;
- input C_N ;
- input D_N ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A ;
+ input B ;
+ input C_N;
+ input D_N;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/o211a/sky130_fd_sc_hdll__o211a_1.v b/cells/o211a/sky130_fd_sc_hdll__o211a_1.v
index 60e06f7..0da742f 100644
--- a/cells/o211a/sky130_fd_sc_hdll__o211a_1.v
+++ b/cells/o211a/sky130_fd_sc_hdll__o211a_1.v
@@ -80,26 +80,18 @@
`celldefine
module sky130_fd_sc_hdll__o211a_1 (
- X ,
- A1 ,
- A2 ,
- B1 ,
- C1 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A1,
+ A2,
+ B1,
+ C1
);
- output X ;
- input A1 ;
- input A2 ;
- input B1 ;
- input C1 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input C1;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/o211a/sky130_fd_sc_hdll__o211a_2.v b/cells/o211a/sky130_fd_sc_hdll__o211a_2.v
index ee932ca..4267706 100644
--- a/cells/o211a/sky130_fd_sc_hdll__o211a_2.v
+++ b/cells/o211a/sky130_fd_sc_hdll__o211a_2.v
@@ -80,26 +80,18 @@
`celldefine
module sky130_fd_sc_hdll__o211a_2 (
- X ,
- A1 ,
- A2 ,
- B1 ,
- C1 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A1,
+ A2,
+ B1,
+ C1
);
- output X ;
- input A1 ;
- input A2 ;
- input B1 ;
- input C1 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input C1;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/o211a/sky130_fd_sc_hdll__o211a_4.v b/cells/o211a/sky130_fd_sc_hdll__o211a_4.v
index d365544..2658272 100644
--- a/cells/o211a/sky130_fd_sc_hdll__o211a_4.v
+++ b/cells/o211a/sky130_fd_sc_hdll__o211a_4.v
@@ -80,26 +80,18 @@
`celldefine
module sky130_fd_sc_hdll__o211a_4 (
- X ,
- A1 ,
- A2 ,
- B1 ,
- C1 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A1,
+ A2,
+ B1,
+ C1
);
- output X ;
- input A1 ;
- input A2 ;
- input B1 ;
- input C1 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input C1;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/o211ai/sky130_fd_sc_hdll__o211ai_1.v b/cells/o211ai/sky130_fd_sc_hdll__o211ai_1.v
index 2dba77e..bc26f08 100644
--- a/cells/o211ai/sky130_fd_sc_hdll__o211ai_1.v
+++ b/cells/o211ai/sky130_fd_sc_hdll__o211ai_1.v
@@ -80,26 +80,18 @@
`celldefine
module sky130_fd_sc_hdll__o211ai_1 (
- Y ,
- A1 ,
- A2 ,
- B1 ,
- C1 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A1,
+ A2,
+ B1,
+ C1
);
- output Y ;
- input A1 ;
- input A2 ;
- input B1 ;
- input C1 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input C1;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/o211ai/sky130_fd_sc_hdll__o211ai_2.v b/cells/o211ai/sky130_fd_sc_hdll__o211ai_2.v
index c806f5c..fdc3f52 100644
--- a/cells/o211ai/sky130_fd_sc_hdll__o211ai_2.v
+++ b/cells/o211ai/sky130_fd_sc_hdll__o211ai_2.v
@@ -80,26 +80,18 @@
`celldefine
module sky130_fd_sc_hdll__o211ai_2 (
- Y ,
- A1 ,
- A2 ,
- B1 ,
- C1 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A1,
+ A2,
+ B1,
+ C1
);
- output Y ;
- input A1 ;
- input A2 ;
- input B1 ;
- input C1 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input C1;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/o211ai/sky130_fd_sc_hdll__o211ai_4.v b/cells/o211ai/sky130_fd_sc_hdll__o211ai_4.v
index d0f86d1..41c827e 100644
--- a/cells/o211ai/sky130_fd_sc_hdll__o211ai_4.v
+++ b/cells/o211ai/sky130_fd_sc_hdll__o211ai_4.v
@@ -80,26 +80,18 @@
`celldefine
module sky130_fd_sc_hdll__o211ai_4 (
- Y ,
- A1 ,
- A2 ,
- B1 ,
- C1 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A1,
+ A2,
+ B1,
+ C1
);
- output Y ;
- input A1 ;
- input A2 ;
- input B1 ;
- input C1 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input C1;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/o21a/sky130_fd_sc_hdll__o21a_1.v b/cells/o21a/sky130_fd_sc_hdll__o21a_1.v
index 5bfbaf8..ec7837b 100644
--- a/cells/o21a/sky130_fd_sc_hdll__o21a_1.v
+++ b/cells/o21a/sky130_fd_sc_hdll__o21a_1.v
@@ -77,24 +77,16 @@
`celldefine
module sky130_fd_sc_hdll__o21a_1 (
- X ,
- A1 ,
- A2 ,
- B1 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A1,
+ A2,
+ B1
);
- output X ;
- input A1 ;
- input A2 ;
- input B1 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A1;
+ input A2;
+ input B1;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/o21a/sky130_fd_sc_hdll__o21a_2.v b/cells/o21a/sky130_fd_sc_hdll__o21a_2.v
index a659da7..13a77a8 100644
--- a/cells/o21a/sky130_fd_sc_hdll__o21a_2.v
+++ b/cells/o21a/sky130_fd_sc_hdll__o21a_2.v
@@ -77,24 +77,16 @@
`celldefine
module sky130_fd_sc_hdll__o21a_2 (
- X ,
- A1 ,
- A2 ,
- B1 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A1,
+ A2,
+ B1
);
- output X ;
- input A1 ;
- input A2 ;
- input B1 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A1;
+ input A2;
+ input B1;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/o21a/sky130_fd_sc_hdll__o21a_4.v b/cells/o21a/sky130_fd_sc_hdll__o21a_4.v
index f7d33d8..aece0e1 100644
--- a/cells/o21a/sky130_fd_sc_hdll__o21a_4.v
+++ b/cells/o21a/sky130_fd_sc_hdll__o21a_4.v
@@ -77,24 +77,16 @@
`celldefine
module sky130_fd_sc_hdll__o21a_4 (
- X ,
- A1 ,
- A2 ,
- B1 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A1,
+ A2,
+ B1
);
- output X ;
- input A1 ;
- input A2 ;
- input B1 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A1;
+ input A2;
+ input B1;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/o21ai/sky130_fd_sc_hdll__o21ai_1.v b/cells/o21ai/sky130_fd_sc_hdll__o21ai_1.v
index 34c77cf..43e5e83 100644
--- a/cells/o21ai/sky130_fd_sc_hdll__o21ai_1.v
+++ b/cells/o21ai/sky130_fd_sc_hdll__o21ai_1.v
@@ -77,24 +77,16 @@
`celldefine
module sky130_fd_sc_hdll__o21ai_1 (
- Y ,
- A1 ,
- A2 ,
- B1 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A1,
+ A2,
+ B1
);
- output Y ;
- input A1 ;
- input A2 ;
- input B1 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/o21ai/sky130_fd_sc_hdll__o21ai_2.v b/cells/o21ai/sky130_fd_sc_hdll__o21ai_2.v
index 007ebf5..3ff3a28 100644
--- a/cells/o21ai/sky130_fd_sc_hdll__o21ai_2.v
+++ b/cells/o21ai/sky130_fd_sc_hdll__o21ai_2.v
@@ -77,24 +77,16 @@
`celldefine
module sky130_fd_sc_hdll__o21ai_2 (
- Y ,
- A1 ,
- A2 ,
- B1 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A1,
+ A2,
+ B1
);
- output Y ;
- input A1 ;
- input A2 ;
- input B1 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/o21ai/sky130_fd_sc_hdll__o21ai_4.v b/cells/o21ai/sky130_fd_sc_hdll__o21ai_4.v
index 37349f1..dcfcc87 100644
--- a/cells/o21ai/sky130_fd_sc_hdll__o21ai_4.v
+++ b/cells/o21ai/sky130_fd_sc_hdll__o21ai_4.v
@@ -77,24 +77,16 @@
`celldefine
module sky130_fd_sc_hdll__o21ai_4 (
- Y ,
- A1 ,
- A2 ,
- B1 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A1,
+ A2,
+ B1
);
- output Y ;
- input A1 ;
- input A2 ;
- input B1 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/o21ba/sky130_fd_sc_hdll__o21ba_1.v b/cells/o21ba/sky130_fd_sc_hdll__o21ba_1.v
index aa09ba4..0ad2264 100644
--- a/cells/o21ba/sky130_fd_sc_hdll__o21ba_1.v
+++ b/cells/o21ba/sky130_fd_sc_hdll__o21ba_1.v
@@ -81,21 +81,13 @@
X ,
A1 ,
A2 ,
- B1_N,
- VPWR,
- VGND,
- VPB ,
- VNB
+ B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/o21ba/sky130_fd_sc_hdll__o21ba_2.v b/cells/o21ba/sky130_fd_sc_hdll__o21ba_2.v
index 04375fe..c74e16b 100644
--- a/cells/o21ba/sky130_fd_sc_hdll__o21ba_2.v
+++ b/cells/o21ba/sky130_fd_sc_hdll__o21ba_2.v
@@ -81,21 +81,13 @@
X ,
A1 ,
A2 ,
- B1_N,
- VPWR,
- VGND,
- VPB ,
- VNB
+ B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/o21ba/sky130_fd_sc_hdll__o21ba_4.v b/cells/o21ba/sky130_fd_sc_hdll__o21ba_4.v
index c31eda9..fb29001 100644
--- a/cells/o21ba/sky130_fd_sc_hdll__o21ba_4.v
+++ b/cells/o21ba/sky130_fd_sc_hdll__o21ba_4.v
@@ -81,21 +81,13 @@
X ,
A1 ,
A2 ,
- B1_N,
- VPWR,
- VGND,
- VPB ,
- VNB
+ B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/o21bai/sky130_fd_sc_hdll__o21bai_1.v b/cells/o21bai/sky130_fd_sc_hdll__o21bai_1.v
index deacd54..9af2b85 100644
--- a/cells/o21bai/sky130_fd_sc_hdll__o21bai_1.v
+++ b/cells/o21bai/sky130_fd_sc_hdll__o21bai_1.v
@@ -81,21 +81,13 @@
Y ,
A1 ,
A2 ,
- B1_N,
- VPWR,
- VGND,
- VPB ,
- VNB
+ B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/o21bai/sky130_fd_sc_hdll__o21bai_2.v b/cells/o21bai/sky130_fd_sc_hdll__o21bai_2.v
index fd69897..4b81542 100644
--- a/cells/o21bai/sky130_fd_sc_hdll__o21bai_2.v
+++ b/cells/o21bai/sky130_fd_sc_hdll__o21bai_2.v
@@ -81,21 +81,13 @@
Y ,
A1 ,
A2 ,
- B1_N,
- VPWR,
- VGND,
- VPB ,
- VNB
+ B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/o21bai/sky130_fd_sc_hdll__o21bai_4.v b/cells/o21bai/sky130_fd_sc_hdll__o21bai_4.v
index 57a8b4e..cf89fd8 100644
--- a/cells/o21bai/sky130_fd_sc_hdll__o21bai_4.v
+++ b/cells/o21bai/sky130_fd_sc_hdll__o21bai_4.v
@@ -81,21 +81,13 @@
Y ,
A1 ,
A2 ,
- B1_N,
- VPWR,
- VGND,
- VPB ,
- VNB
+ B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/o221a/sky130_fd_sc_hdll__o221a_1.v b/cells/o221a/sky130_fd_sc_hdll__o221a_1.v
index f254e31..bfaf1e2 100644
--- a/cells/o221a/sky130_fd_sc_hdll__o221a_1.v
+++ b/cells/o221a/sky130_fd_sc_hdll__o221a_1.v
@@ -83,28 +83,20 @@
`celldefine
module sky130_fd_sc_hdll__o221a_1 (
- X ,
- A1 ,
- A2 ,
- B1 ,
- B2 ,
- C1 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A1,
+ A2,
+ B1,
+ B2,
+ C1
);
- output X ;
- input A1 ;
- input A2 ;
- input B1 ;
- input B2 ;
- input C1 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
+ input C1;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/o221a/sky130_fd_sc_hdll__o221a_2.v b/cells/o221a/sky130_fd_sc_hdll__o221a_2.v
index 829b884..b9d8b9e 100644
--- a/cells/o221a/sky130_fd_sc_hdll__o221a_2.v
+++ b/cells/o221a/sky130_fd_sc_hdll__o221a_2.v
@@ -83,28 +83,20 @@
`celldefine
module sky130_fd_sc_hdll__o221a_2 (
- X ,
- A1 ,
- A2 ,
- B1 ,
- B2 ,
- C1 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A1,
+ A2,
+ B1,
+ B2,
+ C1
);
- output X ;
- input A1 ;
- input A2 ;
- input B1 ;
- input B2 ;
- input C1 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
+ input C1;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/o221a/sky130_fd_sc_hdll__o221a_4.v b/cells/o221a/sky130_fd_sc_hdll__o221a_4.v
index f3c1d04..bf1c03e 100644
--- a/cells/o221a/sky130_fd_sc_hdll__o221a_4.v
+++ b/cells/o221a/sky130_fd_sc_hdll__o221a_4.v
@@ -83,28 +83,20 @@
`celldefine
module sky130_fd_sc_hdll__o221a_4 (
- X ,
- A1 ,
- A2 ,
- B1 ,
- B2 ,
- C1 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A1,
+ A2,
+ B1,
+ B2,
+ C1
);
- output X ;
- input A1 ;
- input A2 ;
- input B1 ;
- input B2 ;
- input C1 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
+ input C1;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/o221ai/sky130_fd_sc_hdll__o221ai_1.v b/cells/o221ai/sky130_fd_sc_hdll__o221ai_1.v
index 47cfcf8..9dea01e 100644
--- a/cells/o221ai/sky130_fd_sc_hdll__o221ai_1.v
+++ b/cells/o221ai/sky130_fd_sc_hdll__o221ai_1.v
@@ -83,28 +83,20 @@
`celldefine
module sky130_fd_sc_hdll__o221ai_1 (
- Y ,
- A1 ,
- A2 ,
- B1 ,
- B2 ,
- C1 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A1,
+ A2,
+ B1,
+ B2,
+ C1
);
- output Y ;
- input A1 ;
- input A2 ;
- input B1 ;
- input B2 ;
- input C1 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
+ input C1;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/o221ai/sky130_fd_sc_hdll__o221ai_2.v b/cells/o221ai/sky130_fd_sc_hdll__o221ai_2.v
index 3c368e8..ac4c7e2 100644
--- a/cells/o221ai/sky130_fd_sc_hdll__o221ai_2.v
+++ b/cells/o221ai/sky130_fd_sc_hdll__o221ai_2.v
@@ -83,28 +83,20 @@
`celldefine
module sky130_fd_sc_hdll__o221ai_2 (
- Y ,
- A1 ,
- A2 ,
- B1 ,
- B2 ,
- C1 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A1,
+ A2,
+ B1,
+ B2,
+ C1
);
- output Y ;
- input A1 ;
- input A2 ;
- input B1 ;
- input B2 ;
- input C1 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
+ input C1;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/o221ai/sky130_fd_sc_hdll__o221ai_4.v b/cells/o221ai/sky130_fd_sc_hdll__o221ai_4.v
index 27afd6e..d572677 100644
--- a/cells/o221ai/sky130_fd_sc_hdll__o221ai_4.v
+++ b/cells/o221ai/sky130_fd_sc_hdll__o221ai_4.v
@@ -83,28 +83,20 @@
`celldefine
module sky130_fd_sc_hdll__o221ai_4 (
- Y ,
- A1 ,
- A2 ,
- B1 ,
- B2 ,
- C1 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A1,
+ A2,
+ B1,
+ B2,
+ C1
);
- output Y ;
- input A1 ;
- input A2 ;
- input B1 ;
- input B2 ;
- input C1 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
+ input C1;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/o22a/sky130_fd_sc_hdll__o22a_1.v b/cells/o22a/sky130_fd_sc_hdll__o22a_1.v
index 959d788..197d128 100644
--- a/cells/o22a/sky130_fd_sc_hdll__o22a_1.v
+++ b/cells/o22a/sky130_fd_sc_hdll__o22a_1.v
@@ -80,26 +80,18 @@
`celldefine
module sky130_fd_sc_hdll__o22a_1 (
- X ,
- A1 ,
- A2 ,
- B1 ,
- B2 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A1,
+ A2,
+ B1,
+ B2
);
- output X ;
- input A1 ;
- input A2 ;
- input B1 ;
- input B2 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/o22a/sky130_fd_sc_hdll__o22a_2.v b/cells/o22a/sky130_fd_sc_hdll__o22a_2.v
index 42f3571..ce2ada3 100644
--- a/cells/o22a/sky130_fd_sc_hdll__o22a_2.v
+++ b/cells/o22a/sky130_fd_sc_hdll__o22a_2.v
@@ -80,26 +80,18 @@
`celldefine
module sky130_fd_sc_hdll__o22a_2 (
- X ,
- A1 ,
- A2 ,
- B1 ,
- B2 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A1,
+ A2,
+ B1,
+ B2
);
- output X ;
- input A1 ;
- input A2 ;
- input B1 ;
- input B2 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/o22a/sky130_fd_sc_hdll__o22a_4.v b/cells/o22a/sky130_fd_sc_hdll__o22a_4.v
index d622221..7a02f1d 100644
--- a/cells/o22a/sky130_fd_sc_hdll__o22a_4.v
+++ b/cells/o22a/sky130_fd_sc_hdll__o22a_4.v
@@ -80,26 +80,18 @@
`celldefine
module sky130_fd_sc_hdll__o22a_4 (
- X ,
- A1 ,
- A2 ,
- B1 ,
- B2 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A1,
+ A2,
+ B1,
+ B2
);
- output X ;
- input A1 ;
- input A2 ;
- input B1 ;
- input B2 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/o22ai/sky130_fd_sc_hdll__o22ai_1.v b/cells/o22ai/sky130_fd_sc_hdll__o22ai_1.v
index d2325f4..0ce93d9 100644
--- a/cells/o22ai/sky130_fd_sc_hdll__o22ai_1.v
+++ b/cells/o22ai/sky130_fd_sc_hdll__o22ai_1.v
@@ -80,26 +80,18 @@
`celldefine
module sky130_fd_sc_hdll__o22ai_1 (
- Y ,
- A1 ,
- A2 ,
- B1 ,
- B2 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A1,
+ A2,
+ B1,
+ B2
);
- output Y ;
- input A1 ;
- input A2 ;
- input B1 ;
- input B2 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/o22ai/sky130_fd_sc_hdll__o22ai_2.v b/cells/o22ai/sky130_fd_sc_hdll__o22ai_2.v
index 6a18553..159ede8 100644
--- a/cells/o22ai/sky130_fd_sc_hdll__o22ai_2.v
+++ b/cells/o22ai/sky130_fd_sc_hdll__o22ai_2.v
@@ -80,26 +80,18 @@
`celldefine
module sky130_fd_sc_hdll__o22ai_2 (
- Y ,
- A1 ,
- A2 ,
- B1 ,
- B2 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A1,
+ A2,
+ B1,
+ B2
);
- output Y ;
- input A1 ;
- input A2 ;
- input B1 ;
- input B2 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/o22ai/sky130_fd_sc_hdll__o22ai_4.v b/cells/o22ai/sky130_fd_sc_hdll__o22ai_4.v
index 3fab697..50a015a 100644
--- a/cells/o22ai/sky130_fd_sc_hdll__o22ai_4.v
+++ b/cells/o22ai/sky130_fd_sc_hdll__o22ai_4.v
@@ -80,26 +80,18 @@
`celldefine
module sky130_fd_sc_hdll__o22ai_4 (
- Y ,
- A1 ,
- A2 ,
- B1 ,
- B2 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A1,
+ A2,
+ B1,
+ B2
);
- output Y ;
- input A1 ;
- input A2 ;
- input B1 ;
- input B2 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/o2bb2a/sky130_fd_sc_hdll__o2bb2a_1.v b/cells/o2bb2a/sky130_fd_sc_hdll__o2bb2a_1.v
index dfc6750..cc1b146 100644
--- a/cells/o2bb2a/sky130_fd_sc_hdll__o2bb2a_1.v
+++ b/cells/o2bb2a/sky130_fd_sc_hdll__o2bb2a_1.v
@@ -84,11 +84,7 @@
A1_N,
A2_N,
B1 ,
- B2 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ B2
);
output X ;
@@ -96,10 +92,6 @@
input A2_N;
input B1 ;
input B2 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/o2bb2a/sky130_fd_sc_hdll__o2bb2a_2.v b/cells/o2bb2a/sky130_fd_sc_hdll__o2bb2a_2.v
index 1b3341c..baf17c6 100644
--- a/cells/o2bb2a/sky130_fd_sc_hdll__o2bb2a_2.v
+++ b/cells/o2bb2a/sky130_fd_sc_hdll__o2bb2a_2.v
@@ -84,11 +84,7 @@
A1_N,
A2_N,
B1 ,
- B2 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ B2
);
output X ;
@@ -96,10 +92,6 @@
input A2_N;
input B1 ;
input B2 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/o2bb2a/sky130_fd_sc_hdll__o2bb2a_4.v b/cells/o2bb2a/sky130_fd_sc_hdll__o2bb2a_4.v
index 457929c..325f8e0 100644
--- a/cells/o2bb2a/sky130_fd_sc_hdll__o2bb2a_4.v
+++ b/cells/o2bb2a/sky130_fd_sc_hdll__o2bb2a_4.v
@@ -84,11 +84,7 @@
A1_N,
A2_N,
B1 ,
- B2 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ B2
);
output X ;
@@ -96,10 +92,6 @@
input A2_N;
input B1 ;
input B2 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/o2bb2ai/sky130_fd_sc_hdll__o2bb2ai_1.v b/cells/o2bb2ai/sky130_fd_sc_hdll__o2bb2ai_1.v
index 812a9e9..67bc949 100644
--- a/cells/o2bb2ai/sky130_fd_sc_hdll__o2bb2ai_1.v
+++ b/cells/o2bb2ai/sky130_fd_sc_hdll__o2bb2ai_1.v
@@ -84,11 +84,7 @@
A1_N,
A2_N,
B1 ,
- B2 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ B2
);
output Y ;
@@ -96,10 +92,6 @@
input A2_N;
input B1 ;
input B2 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/o2bb2ai/sky130_fd_sc_hdll__o2bb2ai_2.v b/cells/o2bb2ai/sky130_fd_sc_hdll__o2bb2ai_2.v
index 8b4d8e1..9e4fa50 100644
--- a/cells/o2bb2ai/sky130_fd_sc_hdll__o2bb2ai_2.v
+++ b/cells/o2bb2ai/sky130_fd_sc_hdll__o2bb2ai_2.v
@@ -84,11 +84,7 @@
A1_N,
A2_N,
B1 ,
- B2 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ B2
);
output Y ;
@@ -96,10 +92,6 @@
input A2_N;
input B1 ;
input B2 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/o2bb2ai/sky130_fd_sc_hdll__o2bb2ai_4.v b/cells/o2bb2ai/sky130_fd_sc_hdll__o2bb2ai_4.v
index 690710a..5cce705 100644
--- a/cells/o2bb2ai/sky130_fd_sc_hdll__o2bb2ai_4.v
+++ b/cells/o2bb2ai/sky130_fd_sc_hdll__o2bb2ai_4.v
@@ -84,11 +84,7 @@
A1_N,
A2_N,
B1 ,
- B2 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ B2
);
output Y ;
@@ -96,10 +92,6 @@
input A2_N;
input B1 ;
input B2 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/o31ai/sky130_fd_sc_hdll__o31ai_1.v b/cells/o31ai/sky130_fd_sc_hdll__o31ai_1.v
index 1e69bf3..a6480e6 100644
--- a/cells/o31ai/sky130_fd_sc_hdll__o31ai_1.v
+++ b/cells/o31ai/sky130_fd_sc_hdll__o31ai_1.v
@@ -80,26 +80,18 @@
`celldefine
module sky130_fd_sc_hdll__o31ai_1 (
- Y ,
- A1 ,
- A2 ,
- A3 ,
- B1 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A1,
+ A2,
+ A3,
+ B1
);
- output Y ;
- input A1 ;
- input A2 ;
- input A3 ;
- input B1 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/o31ai/sky130_fd_sc_hdll__o31ai_2.v b/cells/o31ai/sky130_fd_sc_hdll__o31ai_2.v
index 44fecab..bb1659c 100644
--- a/cells/o31ai/sky130_fd_sc_hdll__o31ai_2.v
+++ b/cells/o31ai/sky130_fd_sc_hdll__o31ai_2.v
@@ -80,26 +80,18 @@
`celldefine
module sky130_fd_sc_hdll__o31ai_2 (
- Y ,
- A1 ,
- A2 ,
- A3 ,
- B1 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A1,
+ A2,
+ A3,
+ B1
);
- output Y ;
- input A1 ;
- input A2 ;
- input A3 ;
- input B1 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/o31ai/sky130_fd_sc_hdll__o31ai_4.v b/cells/o31ai/sky130_fd_sc_hdll__o31ai_4.v
index 51dc743..f5042a9 100644
--- a/cells/o31ai/sky130_fd_sc_hdll__o31ai_4.v
+++ b/cells/o31ai/sky130_fd_sc_hdll__o31ai_4.v
@@ -80,26 +80,18 @@
`celldefine
module sky130_fd_sc_hdll__o31ai_4 (
- Y ,
- A1 ,
- A2 ,
- A3 ,
- B1 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A1,
+ A2,
+ A3,
+ B1
);
- output Y ;
- input A1 ;
- input A2 ;
- input A3 ;
- input B1 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/o32ai/sky130_fd_sc_hdll__o32ai_1.v b/cells/o32ai/sky130_fd_sc_hdll__o32ai_1.v
index 77733ba..3fd314f 100644
--- a/cells/o32ai/sky130_fd_sc_hdll__o32ai_1.v
+++ b/cells/o32ai/sky130_fd_sc_hdll__o32ai_1.v
@@ -83,28 +83,20 @@
`celldefine
module sky130_fd_sc_hdll__o32ai_1 (
- Y ,
- A1 ,
- A2 ,
- A3 ,
- B1 ,
- B2 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A1,
+ A2,
+ A3,
+ B1,
+ B2
);
- output Y ;
- input A1 ;
- input A2 ;
- input A3 ;
- input B1 ;
- input B2 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+ input B2;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/o32ai/sky130_fd_sc_hdll__o32ai_2.v b/cells/o32ai/sky130_fd_sc_hdll__o32ai_2.v
index 6dec6e6..843cce3 100644
--- a/cells/o32ai/sky130_fd_sc_hdll__o32ai_2.v
+++ b/cells/o32ai/sky130_fd_sc_hdll__o32ai_2.v
@@ -83,28 +83,20 @@
`celldefine
module sky130_fd_sc_hdll__o32ai_2 (
- Y ,
- A1 ,
- A2 ,
- A3 ,
- B1 ,
- B2 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A1,
+ A2,
+ A3,
+ B1,
+ B2
);
- output Y ;
- input A1 ;
- input A2 ;
- input A3 ;
- input B1 ;
- input B2 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+ input B2;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/o32ai/sky130_fd_sc_hdll__o32ai_4.v b/cells/o32ai/sky130_fd_sc_hdll__o32ai_4.v
index f1da455..633c564 100644
--- a/cells/o32ai/sky130_fd_sc_hdll__o32ai_4.v
+++ b/cells/o32ai/sky130_fd_sc_hdll__o32ai_4.v
@@ -83,28 +83,20 @@
`celldefine
module sky130_fd_sc_hdll__o32ai_4 (
- Y ,
- A1 ,
- A2 ,
- A3 ,
- B1 ,
- B2 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A1,
+ A2,
+ A3,
+ B1,
+ B2
);
- output Y ;
- input A1 ;
- input A2 ;
- input A3 ;
- input B1 ;
- input B2 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A1;
+ input A2;
+ input A3;
+ input B1;
+ input B2;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/or2/sky130_fd_sc_hdll__or2_1.v b/cells/or2/sky130_fd_sc_hdll__or2_1.v
index 525f6e4..352e776 100644
--- a/cells/or2/sky130_fd_sc_hdll__or2_1.v
+++ b/cells/or2/sky130_fd_sc_hdll__or2_1.v
@@ -72,22 +72,14 @@
`celldefine
module sky130_fd_sc_hdll__or2_1 (
- X ,
- A ,
- B ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A,
+ B
);
- output X ;
- input A ;
- input B ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
+ input B;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/or2/sky130_fd_sc_hdll__or2_2.v b/cells/or2/sky130_fd_sc_hdll__or2_2.v
index d544e8d..bb69e32 100644
--- a/cells/or2/sky130_fd_sc_hdll__or2_2.v
+++ b/cells/or2/sky130_fd_sc_hdll__or2_2.v
@@ -72,22 +72,14 @@
`celldefine
module sky130_fd_sc_hdll__or2_2 (
- X ,
- A ,
- B ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A,
+ B
);
- output X ;
- input A ;
- input B ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
+ input B;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/or2/sky130_fd_sc_hdll__or2_4.v b/cells/or2/sky130_fd_sc_hdll__or2_4.v
index 25069a9..a06d943 100644
--- a/cells/or2/sky130_fd_sc_hdll__or2_4.v
+++ b/cells/or2/sky130_fd_sc_hdll__or2_4.v
@@ -72,22 +72,14 @@
`celldefine
module sky130_fd_sc_hdll__or2_4 (
- X ,
- A ,
- B ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A,
+ B
);
- output X ;
- input A ;
- input B ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
+ input B;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/or2/sky130_fd_sc_hdll__or2_6.v b/cells/or2/sky130_fd_sc_hdll__or2_6.v
index 1ad962e..7a00ef3 100644
--- a/cells/or2/sky130_fd_sc_hdll__or2_6.v
+++ b/cells/or2/sky130_fd_sc_hdll__or2_6.v
@@ -72,22 +72,14 @@
`celldefine
module sky130_fd_sc_hdll__or2_6 (
- X ,
- A ,
- B ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A,
+ B
);
- output X ;
- input A ;
- input B ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
+ input B;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/or2/sky130_fd_sc_hdll__or2_8.v b/cells/or2/sky130_fd_sc_hdll__or2_8.v
index 67069aa..24d0a31 100644
--- a/cells/or2/sky130_fd_sc_hdll__or2_8.v
+++ b/cells/or2/sky130_fd_sc_hdll__or2_8.v
@@ -72,22 +72,14 @@
`celldefine
module sky130_fd_sc_hdll__or2_8 (
- X ,
- A ,
- B ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A,
+ B
);
- output X ;
- input A ;
- input B ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
+ input B;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/or2b/sky130_fd_sc_hdll__or2b_1.v b/cells/or2b/sky130_fd_sc_hdll__or2b_1.v
index 06be038..db0e845 100644
--- a/cells/or2b/sky130_fd_sc_hdll__or2b_1.v
+++ b/cells/or2b/sky130_fd_sc_hdll__or2b_1.v
@@ -72,22 +72,14 @@
`celldefine
module sky130_fd_sc_hdll__or2b_1 (
- X ,
- A ,
- B_N ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A ,
+ B_N
);
- output X ;
- input A ;
- input B_N ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A ;
+ input B_N;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/or2b/sky130_fd_sc_hdll__or2b_2.v b/cells/or2b/sky130_fd_sc_hdll__or2b_2.v
index ee4499e..7773ffd 100644
--- a/cells/or2b/sky130_fd_sc_hdll__or2b_2.v
+++ b/cells/or2b/sky130_fd_sc_hdll__or2b_2.v
@@ -72,22 +72,14 @@
`celldefine
module sky130_fd_sc_hdll__or2b_2 (
- X ,
- A ,
- B_N ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A ,
+ B_N
);
- output X ;
- input A ;
- input B_N ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A ;
+ input B_N;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/or2b/sky130_fd_sc_hdll__or2b_4.v b/cells/or2b/sky130_fd_sc_hdll__or2b_4.v
index 3065b93..5f45866 100644
--- a/cells/or2b/sky130_fd_sc_hdll__or2b_4.v
+++ b/cells/or2b/sky130_fd_sc_hdll__or2b_4.v
@@ -72,22 +72,14 @@
`celldefine
module sky130_fd_sc_hdll__or2b_4 (
- X ,
- A ,
- B_N ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A ,
+ B_N
);
- output X ;
- input A ;
- input B_N ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A ;
+ input B_N;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/or3/sky130_fd_sc_hdll__or3_1.v b/cells/or3/sky130_fd_sc_hdll__or3_1.v
index b65c192..6275180 100644
--- a/cells/or3/sky130_fd_sc_hdll__or3_1.v
+++ b/cells/or3/sky130_fd_sc_hdll__or3_1.v
@@ -75,24 +75,16 @@
`celldefine
module sky130_fd_sc_hdll__or3_1 (
- X ,
- A ,
- B ,
- C ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A,
+ B,
+ C
);
- output X ;
- input A ;
- input B ;
- input C ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
+ input B;
+ input C;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/or3/sky130_fd_sc_hdll__or3_2.v b/cells/or3/sky130_fd_sc_hdll__or3_2.v
index e441bd0..6b80f17 100644
--- a/cells/or3/sky130_fd_sc_hdll__or3_2.v
+++ b/cells/or3/sky130_fd_sc_hdll__or3_2.v
@@ -75,24 +75,16 @@
`celldefine
module sky130_fd_sc_hdll__or3_2 (
- X ,
- A ,
- B ,
- C ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A,
+ B,
+ C
);
- output X ;
- input A ;
- input B ;
- input C ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
+ input B;
+ input C;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/or3/sky130_fd_sc_hdll__or3_4.v b/cells/or3/sky130_fd_sc_hdll__or3_4.v
index 714a00c..648ef1a 100644
--- a/cells/or3/sky130_fd_sc_hdll__or3_4.v
+++ b/cells/or3/sky130_fd_sc_hdll__or3_4.v
@@ -75,24 +75,16 @@
`celldefine
module sky130_fd_sc_hdll__or3_4 (
- X ,
- A ,
- B ,
- C ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A,
+ B,
+ C
);
- output X ;
- input A ;
- input B ;
- input C ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
+ input B;
+ input C;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/or3b/sky130_fd_sc_hdll__or3b_1.v b/cells/or3b/sky130_fd_sc_hdll__or3b_1.v
index 15a31b7..07d17c6 100644
--- a/cells/or3b/sky130_fd_sc_hdll__or3b_1.v
+++ b/cells/or3b/sky130_fd_sc_hdll__or3b_1.v
@@ -75,24 +75,16 @@
`celldefine
module sky130_fd_sc_hdll__or3b_1 (
- X ,
- A ,
- B ,
- C_N ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A ,
+ B ,
+ C_N
);
- output X ;
- input A ;
- input B ;
- input C_N ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A ;
+ input B ;
+ input C_N;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/or3b/sky130_fd_sc_hdll__or3b_2.v b/cells/or3b/sky130_fd_sc_hdll__or3b_2.v
index 420fc03..f29c35a 100644
--- a/cells/or3b/sky130_fd_sc_hdll__or3b_2.v
+++ b/cells/or3b/sky130_fd_sc_hdll__or3b_2.v
@@ -75,24 +75,16 @@
`celldefine
module sky130_fd_sc_hdll__or3b_2 (
- X ,
- A ,
- B ,
- C_N ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A ,
+ B ,
+ C_N
);
- output X ;
- input A ;
- input B ;
- input C_N ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A ;
+ input B ;
+ input C_N;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/or3b/sky130_fd_sc_hdll__or3b_4.v b/cells/or3b/sky130_fd_sc_hdll__or3b_4.v
index ef7a8f8..2cedc05 100644
--- a/cells/or3b/sky130_fd_sc_hdll__or3b_4.v
+++ b/cells/or3b/sky130_fd_sc_hdll__or3b_4.v
@@ -75,24 +75,16 @@
`celldefine
module sky130_fd_sc_hdll__or3b_4 (
- X ,
- A ,
- B ,
- C_N ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A ,
+ B ,
+ C_N
);
- output X ;
- input A ;
- input B ;
- input C_N ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A ;
+ input B ;
+ input C_N;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/or4/sky130_fd_sc_hdll__or4_1.v b/cells/or4/sky130_fd_sc_hdll__or4_1.v
index 5ddea2e..cc4576b 100644
--- a/cells/or4/sky130_fd_sc_hdll__or4_1.v
+++ b/cells/or4/sky130_fd_sc_hdll__or4_1.v
@@ -78,26 +78,18 @@
`celldefine
module sky130_fd_sc_hdll__or4_1 (
- X ,
- A ,
- B ,
- C ,
- D ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A,
+ B,
+ C,
+ D
);
- output X ;
- input A ;
- input B ;
- input C ;
- input D ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
+ input B;
+ input C;
+ input D;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/or4/sky130_fd_sc_hdll__or4_2.v b/cells/or4/sky130_fd_sc_hdll__or4_2.v
index df7340a..3959e30 100644
--- a/cells/or4/sky130_fd_sc_hdll__or4_2.v
+++ b/cells/or4/sky130_fd_sc_hdll__or4_2.v
@@ -78,26 +78,18 @@
`celldefine
module sky130_fd_sc_hdll__or4_2 (
- X ,
- A ,
- B ,
- C ,
- D ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A,
+ B,
+ C,
+ D
);
- output X ;
- input A ;
- input B ;
- input C ;
- input D ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
+ input B;
+ input C;
+ input D;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/or4/sky130_fd_sc_hdll__or4_4.v b/cells/or4/sky130_fd_sc_hdll__or4_4.v
index 71d7336..1f432f6 100644
--- a/cells/or4/sky130_fd_sc_hdll__or4_4.v
+++ b/cells/or4/sky130_fd_sc_hdll__or4_4.v
@@ -78,26 +78,18 @@
`celldefine
module sky130_fd_sc_hdll__or4_4 (
- X ,
- A ,
- B ,
- C ,
- D ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A,
+ B,
+ C,
+ D
);
- output X ;
- input A ;
- input B ;
- input C ;
- input D ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
+ input B;
+ input C;
+ input D;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/or4b/sky130_fd_sc_hdll__or4b_1.v b/cells/or4b/sky130_fd_sc_hdll__or4b_1.v
index 92ca557..8d7122f 100644
--- a/cells/or4b/sky130_fd_sc_hdll__or4b_1.v
+++ b/cells/or4b/sky130_fd_sc_hdll__or4b_1.v
@@ -78,26 +78,18 @@
`celldefine
module sky130_fd_sc_hdll__or4b_1 (
- X ,
- A ,
- B ,
- C ,
- D_N ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A ,
+ B ,
+ C ,
+ D_N
);
- output X ;
- input A ;
- input B ;
- input C ;
- input D_N ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A ;
+ input B ;
+ input C ;
+ input D_N;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/or4b/sky130_fd_sc_hdll__or4b_2.v b/cells/or4b/sky130_fd_sc_hdll__or4b_2.v
index 049acc7..b4e5b72 100644
--- a/cells/or4b/sky130_fd_sc_hdll__or4b_2.v
+++ b/cells/or4b/sky130_fd_sc_hdll__or4b_2.v
@@ -78,26 +78,18 @@
`celldefine
module sky130_fd_sc_hdll__or4b_2 (
- X ,
- A ,
- B ,
- C ,
- D_N ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A ,
+ B ,
+ C ,
+ D_N
);
- output X ;
- input A ;
- input B ;
- input C ;
- input D_N ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A ;
+ input B ;
+ input C ;
+ input D_N;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/or4b/sky130_fd_sc_hdll__or4b_4.v b/cells/or4b/sky130_fd_sc_hdll__or4b_4.v
index 060bfc3..6051d1b 100644
--- a/cells/or4b/sky130_fd_sc_hdll__or4b_4.v
+++ b/cells/or4b/sky130_fd_sc_hdll__or4b_4.v
@@ -78,26 +78,18 @@
`celldefine
module sky130_fd_sc_hdll__or4b_4 (
- X ,
- A ,
- B ,
- C ,
- D_N ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A ,
+ B ,
+ C ,
+ D_N
);
- output X ;
- input A ;
- input B ;
- input C ;
- input D_N ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A ;
+ input B ;
+ input C ;
+ input D_N;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/or4bb/sky130_fd_sc_hdll__or4bb_1.v b/cells/or4bb/sky130_fd_sc_hdll__or4bb_1.v
index 1fc4903..34c1c71 100644
--- a/cells/or4bb/sky130_fd_sc_hdll__or4bb_1.v
+++ b/cells/or4bb/sky130_fd_sc_hdll__or4bb_1.v
@@ -78,26 +78,18 @@
`celldefine
module sky130_fd_sc_hdll__or4bb_1 (
- X ,
- A ,
- B ,
- C_N ,
- D_N ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A ,
+ B ,
+ C_N,
+ D_N
);
- output X ;
- input A ;
- input B ;
- input C_N ;
- input D_N ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A ;
+ input B ;
+ input C_N;
+ input D_N;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/or4bb/sky130_fd_sc_hdll__or4bb_2.v b/cells/or4bb/sky130_fd_sc_hdll__or4bb_2.v
index 67c53bd..8d46bf9 100644
--- a/cells/or4bb/sky130_fd_sc_hdll__or4bb_2.v
+++ b/cells/or4bb/sky130_fd_sc_hdll__or4bb_2.v
@@ -78,26 +78,18 @@
`celldefine
module sky130_fd_sc_hdll__or4bb_2 (
- X ,
- A ,
- B ,
- C_N ,
- D_N ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A ,
+ B ,
+ C_N,
+ D_N
);
- output X ;
- input A ;
- input B ;
- input C_N ;
- input D_N ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A ;
+ input B ;
+ input C_N;
+ input D_N;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/or4bb/sky130_fd_sc_hdll__or4bb_4.v b/cells/or4bb/sky130_fd_sc_hdll__or4bb_4.v
index 64a47f3..2bbdc75 100644
--- a/cells/or4bb/sky130_fd_sc_hdll__or4bb_4.v
+++ b/cells/or4bb/sky130_fd_sc_hdll__or4bb_4.v
@@ -78,26 +78,18 @@
`celldefine
module sky130_fd_sc_hdll__or4bb_4 (
- X ,
- A ,
- B ,
- C_N ,
- D_N ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A ,
+ B ,
+ C_N,
+ D_N
);
- output X ;
- input A ;
- input B ;
- input C_N ;
- input D_N ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A ;
+ input B ;
+ input C_N;
+ input D_N;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/probe_p/sky130_fd_sc_hdll__probe_p_8.v b/cells/probe_p/sky130_fd_sc_hdll__probe_p_8.v
index e9cf573..6a7746e 100644
--- a/cells/probe_p/sky130_fd_sc_hdll__probe_p_8.v
+++ b/cells/probe_p/sky130_fd_sc_hdll__probe_p_8.v
@@ -69,20 +69,12 @@
`celldefine
module sky130_fd_sc_hdll__probe_p_8 (
- X ,
- A ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A
);
- output X ;
- input A ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/probec_p/sky130_fd_sc_hdll__probec_p_8.v b/cells/probec_p/sky130_fd_sc_hdll__probec_p_8.v
index d285b9c..8c819a3 100644
--- a/cells/probec_p/sky130_fd_sc_hdll__probec_p_8.v
+++ b/cells/probec_p/sky130_fd_sc_hdll__probec_p_8.v
@@ -69,20 +69,12 @@
`celldefine
module sky130_fd_sc_hdll__probec_p_8 (
- X ,
- A ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A
);
- output X ;
- input A ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/sdfbbp/sky130_fd_sc_hdll__sdfbbp_1.v b/cells/sdfbbp/sky130_fd_sc_hdll__sdfbbp_1.v
index 74d0765..6b2ca58 100644
--- a/cells/sdfbbp/sky130_fd_sc_hdll__sdfbbp_1.v
+++ b/cells/sdfbbp/sky130_fd_sc_hdll__sdfbbp_1.v
@@ -95,11 +95,7 @@
SCE ,
CLK ,
SET_B ,
- RESET_B,
- VPWR ,
- VGND ,
- VPB ,
- VNB
+ RESET_B
);
output Q ;
@@ -110,10 +106,6 @@
input CLK ;
input SET_B ;
input RESET_B;
- input VPWR ;
- input VGND ;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/sdfrbp/sky130_fd_sc_hdll__sdfrbp_1.v b/cells/sdfrbp/sky130_fd_sc_hdll__sdfrbp_1.v
index b8762a3..5d6770f 100644
--- a/cells/sdfrbp/sky130_fd_sc_hdll__sdfrbp_1.v
+++ b/cells/sdfrbp/sky130_fd_sc_hdll__sdfrbp_1.v
@@ -91,11 +91,7 @@
D ,
SCD ,
SCE ,
- RESET_B,
- VPWR ,
- VGND ,
- VPB ,
- VNB
+ RESET_B
);
output Q ;
@@ -105,10 +101,6 @@
input SCD ;
input SCE ;
input RESET_B;
- input VPWR ;
- input VGND ;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/sdfrbp/sky130_fd_sc_hdll__sdfrbp_2.v b/cells/sdfrbp/sky130_fd_sc_hdll__sdfrbp_2.v
index abe35e9..57b2eb9 100644
--- a/cells/sdfrbp/sky130_fd_sc_hdll__sdfrbp_2.v
+++ b/cells/sdfrbp/sky130_fd_sc_hdll__sdfrbp_2.v
@@ -91,11 +91,7 @@
D ,
SCD ,
SCE ,
- RESET_B,
- VPWR ,
- VGND ,
- VPB ,
- VNB
+ RESET_B
);
output Q ;
@@ -105,10 +101,6 @@
input SCD ;
input SCE ;
input RESET_B;
- input VPWR ;
- input VGND ;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/sdfrtn/sky130_fd_sc_hdll__sdfrtn_1.v b/cells/sdfrtn/sky130_fd_sc_hdll__sdfrtn_1.v
index 4b7d863..89d93e5 100644
--- a/cells/sdfrtn/sky130_fd_sc_hdll__sdfrtn_1.v
+++ b/cells/sdfrtn/sky130_fd_sc_hdll__sdfrtn_1.v
@@ -87,11 +87,7 @@
D ,
SCD ,
SCE ,
- RESET_B,
- VPWR ,
- VGND ,
- VPB ,
- VNB
+ RESET_B
);
output Q ;
@@ -100,10 +96,6 @@
input SCD ;
input SCE ;
input RESET_B;
- input VPWR ;
- input VGND ;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/sdfrtp/sky130_fd_sc_hdll__sdfrtp_1.v b/cells/sdfrtp/sky130_fd_sc_hdll__sdfrtp_1.v
index 16ad3c4..208ddf3 100644
--- a/cells/sdfrtp/sky130_fd_sc_hdll__sdfrtp_1.v
+++ b/cells/sdfrtp/sky130_fd_sc_hdll__sdfrtp_1.v
@@ -87,11 +87,7 @@
D ,
SCD ,
SCE ,
- RESET_B,
- VPWR ,
- VGND ,
- VPB ,
- VNB
+ RESET_B
);
output Q ;
@@ -100,10 +96,6 @@
input SCD ;
input SCE ;
input RESET_B;
- input VPWR ;
- input VGND ;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/sdfrtp/sky130_fd_sc_hdll__sdfrtp_2.v b/cells/sdfrtp/sky130_fd_sc_hdll__sdfrtp_2.v
index 9450d72..d76bfb3 100644
--- a/cells/sdfrtp/sky130_fd_sc_hdll__sdfrtp_2.v
+++ b/cells/sdfrtp/sky130_fd_sc_hdll__sdfrtp_2.v
@@ -87,11 +87,7 @@
D ,
SCD ,
SCE ,
- RESET_B,
- VPWR ,
- VGND ,
- VPB ,
- VNB
+ RESET_B
);
output Q ;
@@ -100,10 +96,6 @@
input SCD ;
input SCE ;
input RESET_B;
- input VPWR ;
- input VGND ;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/sdfrtp/sky130_fd_sc_hdll__sdfrtp_4.v b/cells/sdfrtp/sky130_fd_sc_hdll__sdfrtp_4.v
index bf4d3b6..79e9e65 100644
--- a/cells/sdfrtp/sky130_fd_sc_hdll__sdfrtp_4.v
+++ b/cells/sdfrtp/sky130_fd_sc_hdll__sdfrtp_4.v
@@ -87,11 +87,7 @@
D ,
SCD ,
SCE ,
- RESET_B,
- VPWR ,
- VGND ,
- VPB ,
- VNB
+ RESET_B
);
output Q ;
@@ -100,10 +96,6 @@
input SCD ;
input SCE ;
input RESET_B;
- input VPWR ;
- input VGND ;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/sdfsbp/sky130_fd_sc_hdll__sdfsbp_1.v b/cells/sdfsbp/sky130_fd_sc_hdll__sdfsbp_1.v
index 86891de..8102737 100644
--- a/cells/sdfsbp/sky130_fd_sc_hdll__sdfsbp_1.v
+++ b/cells/sdfsbp/sky130_fd_sc_hdll__sdfsbp_1.v
@@ -91,11 +91,7 @@
D ,
SCD ,
SCE ,
- SET_B,
- VPWR ,
- VGND ,
- VPB ,
- VNB
+ SET_B
);
output Q ;
@@ -105,10 +101,6 @@
input SCD ;
input SCE ;
input SET_B;
- input VPWR ;
- input VGND ;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/sdfsbp/sky130_fd_sc_hdll__sdfsbp_2.v b/cells/sdfsbp/sky130_fd_sc_hdll__sdfsbp_2.v
index ab92581..6d52c32 100644
--- a/cells/sdfsbp/sky130_fd_sc_hdll__sdfsbp_2.v
+++ b/cells/sdfsbp/sky130_fd_sc_hdll__sdfsbp_2.v
@@ -91,11 +91,7 @@
D ,
SCD ,
SCE ,
- SET_B,
- VPWR ,
- VGND ,
- VPB ,
- VNB
+ SET_B
);
output Q ;
@@ -105,10 +101,6 @@
input SCD ;
input SCE ;
input SET_B;
- input VPWR ;
- input VGND ;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/sdfstp/sky130_fd_sc_hdll__sdfstp_1.v b/cells/sdfstp/sky130_fd_sc_hdll__sdfstp_1.v
index 62db623..2b7822c 100644
--- a/cells/sdfstp/sky130_fd_sc_hdll__sdfstp_1.v
+++ b/cells/sdfstp/sky130_fd_sc_hdll__sdfstp_1.v
@@ -87,11 +87,7 @@
D ,
SCD ,
SCE ,
- SET_B,
- VPWR ,
- VGND ,
- VPB ,
- VNB
+ SET_B
);
output Q ;
@@ -100,10 +96,6 @@
input SCD ;
input SCE ;
input SET_B;
- input VPWR ;
- input VGND ;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/sdfstp/sky130_fd_sc_hdll__sdfstp_2.v b/cells/sdfstp/sky130_fd_sc_hdll__sdfstp_2.v
index 9d0d7be..b5e0590 100644
--- a/cells/sdfstp/sky130_fd_sc_hdll__sdfstp_2.v
+++ b/cells/sdfstp/sky130_fd_sc_hdll__sdfstp_2.v
@@ -87,11 +87,7 @@
D ,
SCD ,
SCE ,
- SET_B,
- VPWR ,
- VGND ,
- VPB ,
- VNB
+ SET_B
);
output Q ;
@@ -100,10 +96,6 @@
input SCD ;
input SCE ;
input SET_B;
- input VPWR ;
- input VGND ;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/sdfstp/sky130_fd_sc_hdll__sdfstp_4.v b/cells/sdfstp/sky130_fd_sc_hdll__sdfstp_4.v
index a0d40ba..18524b6 100644
--- a/cells/sdfstp/sky130_fd_sc_hdll__sdfstp_4.v
+++ b/cells/sdfstp/sky130_fd_sc_hdll__sdfstp_4.v
@@ -87,11 +87,7 @@
D ,
SCD ,
SCE ,
- SET_B,
- VPWR ,
- VGND ,
- VPB ,
- VNB
+ SET_B
);
output Q ;
@@ -100,10 +96,6 @@
input SCD ;
input SCE ;
input SET_B;
- input VPWR ;
- input VGND ;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/sdfxbp/sky130_fd_sc_hdll__sdfxbp_1.v b/cells/sdfxbp/sky130_fd_sc_hdll__sdfxbp_1.v
index c7a6019..e36dcd2 100644
--- a/cells/sdfxbp/sky130_fd_sc_hdll__sdfxbp_1.v
+++ b/cells/sdfxbp/sky130_fd_sc_hdll__sdfxbp_1.v
@@ -81,28 +81,20 @@
`celldefine
module sky130_fd_sc_hdll__sdfxbp_1 (
- Q ,
- Q_N ,
- CLK ,
- D ,
- SCD ,
- SCE ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Q ,
+ Q_N,
+ CLK,
+ D ,
+ SCD,
+ SCE
);
- output Q ;
- output Q_N ;
- input CLK ;
- input D ;
- input SCD ;
- input SCE ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Q ;
+ output Q_N;
+ input CLK;
+ input D ;
+ input SCD;
+ input SCE;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/sdfxbp/sky130_fd_sc_hdll__sdfxbp_2.v b/cells/sdfxbp/sky130_fd_sc_hdll__sdfxbp_2.v
index 42955fd..012912a 100644
--- a/cells/sdfxbp/sky130_fd_sc_hdll__sdfxbp_2.v
+++ b/cells/sdfxbp/sky130_fd_sc_hdll__sdfxbp_2.v
@@ -81,28 +81,20 @@
`celldefine
module sky130_fd_sc_hdll__sdfxbp_2 (
- Q ,
- Q_N ,
- CLK ,
- D ,
- SCD ,
- SCE ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Q ,
+ Q_N,
+ CLK,
+ D ,
+ SCD,
+ SCE
);
- output Q ;
- output Q_N ;
- input CLK ;
- input D ;
- input SCD ;
- input SCE ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Q ;
+ output Q_N;
+ input CLK;
+ input D ;
+ input SCD;
+ input SCE;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/sdfxtp/sky130_fd_sc_hdll__sdfxtp_1.v b/cells/sdfxtp/sky130_fd_sc_hdll__sdfxtp_1.v
index bcdadf6..694c6d5 100644
--- a/cells/sdfxtp/sky130_fd_sc_hdll__sdfxtp_1.v
+++ b/cells/sdfxtp/sky130_fd_sc_hdll__sdfxtp_1.v
@@ -78,26 +78,18 @@
`celldefine
module sky130_fd_sc_hdll__sdfxtp_1 (
- Q ,
- CLK ,
- D ,
- SCD ,
- SCE ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Q ,
+ CLK,
+ D ,
+ SCD,
+ SCE
);
- output Q ;
- input CLK ;
- input D ;
- input SCD ;
- input SCE ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Q ;
+ input CLK;
+ input D ;
+ input SCD;
+ input SCE;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/sdfxtp/sky130_fd_sc_hdll__sdfxtp_2.v b/cells/sdfxtp/sky130_fd_sc_hdll__sdfxtp_2.v
index 5a385ba..be79af6 100644
--- a/cells/sdfxtp/sky130_fd_sc_hdll__sdfxtp_2.v
+++ b/cells/sdfxtp/sky130_fd_sc_hdll__sdfxtp_2.v
@@ -78,26 +78,18 @@
`celldefine
module sky130_fd_sc_hdll__sdfxtp_2 (
- Q ,
- CLK ,
- D ,
- SCD ,
- SCE ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Q ,
+ CLK,
+ D ,
+ SCD,
+ SCE
);
- output Q ;
- input CLK ;
- input D ;
- input SCD ;
- input SCE ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Q ;
+ input CLK;
+ input D ;
+ input SCD;
+ input SCE;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/sdfxtp/sky130_fd_sc_hdll__sdfxtp_4.v b/cells/sdfxtp/sky130_fd_sc_hdll__sdfxtp_4.v
index 2afab49..bb53456 100644
--- a/cells/sdfxtp/sky130_fd_sc_hdll__sdfxtp_4.v
+++ b/cells/sdfxtp/sky130_fd_sc_hdll__sdfxtp_4.v
@@ -78,26 +78,18 @@
`celldefine
module sky130_fd_sc_hdll__sdfxtp_4 (
- Q ,
- CLK ,
- D ,
- SCD ,
- SCE ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Q ,
+ CLK,
+ D ,
+ SCD,
+ SCE
);
- output Q ;
- input CLK ;
- input D ;
- input SCD ;
- input SCE ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Q ;
+ input CLK;
+ input D ;
+ input SCD;
+ input SCE;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/sdlclkp/sky130_fd_sc_hdll__sdlclkp_1.v b/cells/sdlclkp/sky130_fd_sc_hdll__sdlclkp_1.v
index 394666d..b53cef0 100644
--- a/cells/sdlclkp/sky130_fd_sc_hdll__sdlclkp_1.v
+++ b/cells/sdlclkp/sky130_fd_sc_hdll__sdlclkp_1.v
@@ -78,21 +78,13 @@
GCLK,
SCE ,
GATE,
- CLK ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ CLK
);
output GCLK;
input SCE ;
input GATE;
input CLK ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/sdlclkp/sky130_fd_sc_hdll__sdlclkp_2.v b/cells/sdlclkp/sky130_fd_sc_hdll__sdlclkp_2.v
index b595c5f..2c4c982 100644
--- a/cells/sdlclkp/sky130_fd_sc_hdll__sdlclkp_2.v
+++ b/cells/sdlclkp/sky130_fd_sc_hdll__sdlclkp_2.v
@@ -78,21 +78,13 @@
GCLK,
SCE ,
GATE,
- CLK ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ CLK
);
output GCLK;
input SCE ;
input GATE;
input CLK ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/sdlclkp/sky130_fd_sc_hdll__sdlclkp_4.v b/cells/sdlclkp/sky130_fd_sc_hdll__sdlclkp_4.v
index c6e6c5e..0d58af2 100644
--- a/cells/sdlclkp/sky130_fd_sc_hdll__sdlclkp_4.v
+++ b/cells/sdlclkp/sky130_fd_sc_hdll__sdlclkp_4.v
@@ -78,21 +78,13 @@
GCLK,
SCE ,
GATE,
- CLK ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ CLK
);
output GCLK;
input SCE ;
input GATE;
input CLK ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/sedfxbp/sky130_fd_sc_hdll__sedfxbp_1.v b/cells/sedfxbp/sky130_fd_sc_hdll__sedfxbp_1.v
index 7f2746d..76c7100 100644
--- a/cells/sedfxbp/sky130_fd_sc_hdll__sedfxbp_1.v
+++ b/cells/sedfxbp/sky130_fd_sc_hdll__sedfxbp_1.v
@@ -85,30 +85,22 @@
`celldefine
module sky130_fd_sc_hdll__sedfxbp_1 (
- Q ,
- Q_N ,
- CLK ,
- D ,
- DE ,
- SCD ,
- SCE ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Q ,
+ Q_N,
+ CLK,
+ D ,
+ DE ,
+ SCD,
+ SCE
);
- output Q ;
- output Q_N ;
- input CLK ;
- input D ;
- input DE ;
- input SCD ;
- input SCE ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Q ;
+ output Q_N;
+ input CLK;
+ input D ;
+ input DE ;
+ input SCD;
+ input SCE;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/sedfxbp/sky130_fd_sc_hdll__sedfxbp_2.v b/cells/sedfxbp/sky130_fd_sc_hdll__sedfxbp_2.v
index 02681d2..31a3866 100644
--- a/cells/sedfxbp/sky130_fd_sc_hdll__sedfxbp_2.v
+++ b/cells/sedfxbp/sky130_fd_sc_hdll__sedfxbp_2.v
@@ -85,30 +85,22 @@
`celldefine
module sky130_fd_sc_hdll__sedfxbp_2 (
- Q ,
- Q_N ,
- CLK ,
- D ,
- DE ,
- SCD ,
- SCE ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Q ,
+ Q_N,
+ CLK,
+ D ,
+ DE ,
+ SCD,
+ SCE
);
- output Q ;
- output Q_N ;
- input CLK ;
- input D ;
- input DE ;
- input SCD ;
- input SCE ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Q ;
+ output Q_N;
+ input CLK;
+ input D ;
+ input DE ;
+ input SCD;
+ input SCE;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/tap/sky130_fd_sc_hdll__tap_1.v b/cells/tap/sky130_fd_sc_hdll__tap_1.v
index 727320d..36ecf51 100644
--- a/cells/tap/sky130_fd_sc_hdll__tap_1.v
+++ b/cells/tap/sky130_fd_sc_hdll__tap_1.v
@@ -62,18 +62,7 @@
/*********************************************************/
`celldefine
-module sky130_fd_sc_hdll__tap_1 (
- VPWR,
- VGND,
- VPB ,
- VNB
-);
-
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
-
+module sky130_fd_sc_hdll__tap_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
diff --git a/cells/tapvgnd/sky130_fd_sc_hdll__tapvgnd_1.v b/cells/tapvgnd/sky130_fd_sc_hdll__tapvgnd_1.v
index ddb98ff..4a01bc2 100644
--- a/cells/tapvgnd/sky130_fd_sc_hdll__tapvgnd_1.v
+++ b/cells/tapvgnd/sky130_fd_sc_hdll__tapvgnd_1.v
@@ -63,18 +63,7 @@
/*********************************************************/
`celldefine
-module sky130_fd_sc_hdll__tapvgnd_1 (
- VPWR,
- VGND,
- VPB ,
- VNB
-);
-
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
-
+module sky130_fd_sc_hdll__tapvgnd_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
diff --git a/cells/tapvgnd2/sky130_fd_sc_hdll__tapvgnd2_1.v b/cells/tapvgnd2/sky130_fd_sc_hdll__tapvgnd2_1.v
index 5d66e6e..46313ee 100644
--- a/cells/tapvgnd2/sky130_fd_sc_hdll__tapvgnd2_1.v
+++ b/cells/tapvgnd2/sky130_fd_sc_hdll__tapvgnd2_1.v
@@ -63,18 +63,7 @@
/*********************************************************/
`celldefine
-module sky130_fd_sc_hdll__tapvgnd2_1 (
- VPWR,
- VGND,
- VPB ,
- VNB
-);
-
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
-
+module sky130_fd_sc_hdll__tapvgnd2_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
diff --git a/cells/tapvpwrvgnd/sky130_fd_sc_hdll__tapvpwrvgnd_1.v b/cells/tapvpwrvgnd/sky130_fd_sc_hdll__tapvpwrvgnd_1.v
index bd92bb2..3ebc6e8 100644
--- a/cells/tapvpwrvgnd/sky130_fd_sc_hdll__tapvpwrvgnd_1.v
+++ b/cells/tapvpwrvgnd/sky130_fd_sc_hdll__tapvpwrvgnd_1.v
@@ -62,18 +62,7 @@
/*********************************************************/
`celldefine
-module sky130_fd_sc_hdll__tapvpwrvgnd_1 (
- VPWR,
- VGND,
- VPB ,
- VNB
-);
-
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
-
+module sky130_fd_sc_hdll__tapvpwrvgnd_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
diff --git a/cells/xnor2/sky130_fd_sc_hdll__xnor2_1.v b/cells/xnor2/sky130_fd_sc_hdll__xnor2_1.v
index c15c5dc..cdd1b40 100644
--- a/cells/xnor2/sky130_fd_sc_hdll__xnor2_1.v
+++ b/cells/xnor2/sky130_fd_sc_hdll__xnor2_1.v
@@ -74,22 +74,14 @@
`celldefine
module sky130_fd_sc_hdll__xnor2_1 (
- Y ,
- A ,
- B ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A,
+ B
);
- output Y ;
- input A ;
- input B ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
+ input B;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/xnor2/sky130_fd_sc_hdll__xnor2_2.v b/cells/xnor2/sky130_fd_sc_hdll__xnor2_2.v
index c038d91..088a50a 100644
--- a/cells/xnor2/sky130_fd_sc_hdll__xnor2_2.v
+++ b/cells/xnor2/sky130_fd_sc_hdll__xnor2_2.v
@@ -74,22 +74,14 @@
`celldefine
module sky130_fd_sc_hdll__xnor2_2 (
- Y ,
- A ,
- B ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A,
+ B
);
- output Y ;
- input A ;
- input B ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
+ input B;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/xnor2/sky130_fd_sc_hdll__xnor2_4.v b/cells/xnor2/sky130_fd_sc_hdll__xnor2_4.v
index 408719d..434e8cb 100644
--- a/cells/xnor2/sky130_fd_sc_hdll__xnor2_4.v
+++ b/cells/xnor2/sky130_fd_sc_hdll__xnor2_4.v
@@ -74,22 +74,14 @@
`celldefine
module sky130_fd_sc_hdll__xnor2_4 (
- Y ,
- A ,
- B ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A,
+ B
);
- output Y ;
- input A ;
- input B ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
+ input B;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/xnor3/sky130_fd_sc_hdll__xnor3_1.v b/cells/xnor3/sky130_fd_sc_hdll__xnor3_1.v
index 31d1853..67d1ac5 100644
--- a/cells/xnor3/sky130_fd_sc_hdll__xnor3_1.v
+++ b/cells/xnor3/sky130_fd_sc_hdll__xnor3_1.v
@@ -75,24 +75,16 @@
`celldefine
module sky130_fd_sc_hdll__xnor3_1 (
- X ,
- A ,
- B ,
- C ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A,
+ B,
+ C
);
- output X ;
- input A ;
- input B ;
- input C ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
+ input B;
+ input C;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/xnor3/sky130_fd_sc_hdll__xnor3_2.v b/cells/xnor3/sky130_fd_sc_hdll__xnor3_2.v
index 495fe80..593a27c 100644
--- a/cells/xnor3/sky130_fd_sc_hdll__xnor3_2.v
+++ b/cells/xnor3/sky130_fd_sc_hdll__xnor3_2.v
@@ -75,24 +75,16 @@
`celldefine
module sky130_fd_sc_hdll__xnor3_2 (
- X ,
- A ,
- B ,
- C ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A,
+ B,
+ C
);
- output X ;
- input A ;
- input B ;
- input C ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
+ input B;
+ input C;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/xnor3/sky130_fd_sc_hdll__xnor3_4.v b/cells/xnor3/sky130_fd_sc_hdll__xnor3_4.v
index bc2ba45..c673699 100644
--- a/cells/xnor3/sky130_fd_sc_hdll__xnor3_4.v
+++ b/cells/xnor3/sky130_fd_sc_hdll__xnor3_4.v
@@ -75,24 +75,16 @@
`celldefine
module sky130_fd_sc_hdll__xnor3_4 (
- X ,
- A ,
- B ,
- C ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A,
+ B,
+ C
);
- output X ;
- input A ;
- input B ;
- input C ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
+ input B;
+ input C;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/xor2/sky130_fd_sc_hdll__xor2_1.v b/cells/xor2/sky130_fd_sc_hdll__xor2_1.v
index 8097e8e..20a4f3a 100644
--- a/cells/xor2/sky130_fd_sc_hdll__xor2_1.v
+++ b/cells/xor2/sky130_fd_sc_hdll__xor2_1.v
@@ -74,22 +74,14 @@
`celldefine
module sky130_fd_sc_hdll__xor2_1 (
- X ,
- A ,
- B ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A,
+ B
);
- output X ;
- input A ;
- input B ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
+ input B;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/xor2/sky130_fd_sc_hdll__xor2_2.v b/cells/xor2/sky130_fd_sc_hdll__xor2_2.v
index 5fec481..3601028 100644
--- a/cells/xor2/sky130_fd_sc_hdll__xor2_2.v
+++ b/cells/xor2/sky130_fd_sc_hdll__xor2_2.v
@@ -74,22 +74,14 @@
`celldefine
module sky130_fd_sc_hdll__xor2_2 (
- X ,
- A ,
- B ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A,
+ B
);
- output X ;
- input A ;
- input B ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
+ input B;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/xor2/sky130_fd_sc_hdll__xor2_4.v b/cells/xor2/sky130_fd_sc_hdll__xor2_4.v
index 46e361e..f6a6a8d 100644
--- a/cells/xor2/sky130_fd_sc_hdll__xor2_4.v
+++ b/cells/xor2/sky130_fd_sc_hdll__xor2_4.v
@@ -74,22 +74,14 @@
`celldefine
module sky130_fd_sc_hdll__xor2_4 (
- X ,
- A ,
- B ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A,
+ B
);
- output X ;
- input A ;
- input B ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
+ input B;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/xor3/sky130_fd_sc_hdll__xor3_1.v b/cells/xor3/sky130_fd_sc_hdll__xor3_1.v
index a11896a..c017748 100644
--- a/cells/xor3/sky130_fd_sc_hdll__xor3_1.v
+++ b/cells/xor3/sky130_fd_sc_hdll__xor3_1.v
@@ -77,24 +77,16 @@
`celldefine
module sky130_fd_sc_hdll__xor3_1 (
- X ,
- A ,
- B ,
- C ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A,
+ B,
+ C
);
- output X ;
- input A ;
- input B ;
- input C ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
+ input B;
+ input C;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/xor3/sky130_fd_sc_hdll__xor3_2.v b/cells/xor3/sky130_fd_sc_hdll__xor3_2.v
index 536492e..ee4aae3 100644
--- a/cells/xor3/sky130_fd_sc_hdll__xor3_2.v
+++ b/cells/xor3/sky130_fd_sc_hdll__xor3_2.v
@@ -77,24 +77,16 @@
`celldefine
module sky130_fd_sc_hdll__xor3_2 (
- X ,
- A ,
- B ,
- C ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A,
+ B,
+ C
);
- output X ;
- input A ;
- input B ;
- input C ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
+ input B;
+ input C;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/xor3/sky130_fd_sc_hdll__xor3_4.v b/cells/xor3/sky130_fd_sc_hdll__xor3_4.v
index acfbe57..d0e59c4 100644
--- a/cells/xor3/sky130_fd_sc_hdll__xor3_4.v
+++ b/cells/xor3/sky130_fd_sc_hdll__xor3_4.v
@@ -77,24 +77,16 @@
`celldefine
module sky130_fd_sc_hdll__xor3_4 (
- X ,
- A ,
- B ,
- C ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A,
+ B,
+ C
);
- output X ;
- input A ;
- input B ;
- input C ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
+ input B;
+ input C;
// Voltage supply signals
supply1 VPWR;
