{
  "area": 21.2704,
  "cell_footprint": "sky130_fd_sc_hdll__sdlclkp",
  "cell_leakage_power": 0.0,
  "clock_gating_integrated_cell": "latch_posedge_precontrol",
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    "pg_type": "primary_ground",
    "related_bias_pin": "VPB",
    "voltage_name": "VGND"
  },
  "pg_pin,VNB": {
    "pg_type": "nwell",
    "physical_connection": "device_layer",
    "voltage_name": "VNB"
  },
  "pg_pin,VPB": {
    "pg_type": "pwell",
    "physical_connection": "device_layer",
    "voltage_name": "VPB"
  },
  "pg_pin,VPWR": {
    "pg_type": "primary_power",
    "related_bias_pin": "VNB",
    "voltage_name": "VPWR"
  },
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    "clock_gate_clock_pin": "true",
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      "rise_power,power_inputs_1": {
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    "max_transition": 5.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.003256,
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      "related_pin": "CLK",
      "sim_opt": "runlvl=5 accurate=1",
      "timing_type": "min_pulse_width",
      "violation_delay_degrade_pct": 10.0
    }
  },
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    "clock": "false",
    "clock_gate_enable_pin": "true",
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    "fall_capacitance": 0.00152,
    "internal_power": {
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      "rise_power,power_inputs_1": {
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    "max_transition": 5.0,
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        "related_pin": "CLK",
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              0.6941387
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        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_rising",
        "violation_delay_degrade_pct": 10.0
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      {
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        },
        "related_pin": "CLK",
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        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10.0
      }
    ]
  },
  "pin,GCLK": {
    "clock_gate_out_pin": "true",
    "direction": "output",
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        "related_pin": "CLK",
        "rise_power,power_outputs_1": {
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        "when": "(!GATE&SCE)"
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      {
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        "related_pin": "CLK",
        "rise_power,power_outputs_1": {
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        "when": "(GATE&!SCE)"
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      {
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        "when": "(GATE&SCE)"
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      {
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        "rise_power,scalar": {
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        "when": "(!GATE&!SCE)"
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    "max_capacitance": 0.238619,
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    "power_down_function": "(!VPWR + VGND)",
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "state_function": "(CLK*M0)",
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        "cell_rise,del_1_7_7": {
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            0.0013977,
            0.0039073,
            0.0109229,
            0.0305347,
            0.085359,
            0.238619
          ],
          "values": [
            [
              0.0894319,
              0.0958505,
              0.1128444,
              0.1545423,
              0.2523815,
              0.521519,
              1.3401549
            ],
            [
              0.0894708,
              0.0966922,
              0.1128923,
              0.1524848,
              0.2523631,
              0.5215207,
              1.3371131
            ],
            [
              0.0894527,
              0.0958414,
              0.112869,
              0.1545588,
              0.2522899,
              0.5214622,
              1.3402538
            ],
            [
              0.0891212,
              0.0969457,
              0.1128094,
              0.1543952,
              0.25191,
              0.5210872,
              1.3365775
            ],
            [
              0.0898169,
              0.0959368,
              0.1131377,
              0.1524975,
              0.251721,
              0.5203326,
              1.3372875
            ],
            [
              0.0894224,
              0.0960681,
              0.113256,
              0.1530037,
              0.2519018,
              0.520222,
              1.3398071
            ],
            [
              0.1205178,
              0.1271374,
              0.1436818,
              0.1834599,
              0.2701683,
              0.5291316,
              1.3379943
            ]
          ]
        },
        "related_pin": "CLK",
        "sdf_cond": "GATE==1'b0&&SCE==1'b0",
        "timing_sense": "positive_unate",
        "timing_type": "combinational_fall",
        "when": "(!GATE&!SCE)"
      }
    ]
  },
  "pin,M0": {
    "direction": "internal",
    "internal_node": "M0",
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR"
  },
  "pin,SCE": {
    "capacitance": 0.00156,
    "clock": "false",
    "clock_gate_test_pin": "true",
    "direction": "input",
    "fall_capacitance": 0.001424,
    "internal_power": {
      "fall_power,power_inputs_1": {
        "index_1": [
          0.01,
          0.0281727,
          0.0793701,
          0.223607,
          0.629961,
          1.77477,
          4.9999998
        ],
        "values": [
          0.0044628,
          0.0043959,
          0.0042072,
          0.0045432,
          0.0054896,
          0.0081559,
          0.0156676
        ]
      },
      "rise_power,power_inputs_1": {
        "index_1": [
          0.01,
          0.0281727,
          0.0793701,
          0.223607,
          0.629961,
          1.77477,
          4.9999998
        ],
        "values": [
          0.0096495,
          0.0093845,
          0.008638,
          0.0086674,
          0.0087503,
          0.0089838,
          0.0096415
        ]
      }
    },
    "max_transition": 5.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.001695,
    "timing": [
      {
        "fall_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
            2.5,
            5.0
          ],
          "index_2": [
            0.01,
            2.5,
            5.0
          ],
          "values": [
            [
              1.0511943,
              2.1518048,
              3.2406718
            ],
            [
              0.1629863,
              1.2599345,
              2.3433087
            ],
            [
              -0.4571309,
              0.6361553,
              1.7195293
            ]
          ]
        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
            2.5,
            5.0
          ],
          "index_2": [
            0.01,
            2.5,
            5.0
          ],
          "values": [
            [
              0.3499004,
              1.2344463,
              1.9387921
            ],
            [
              -0.3332295,
              0.5330059,
              1.2172099
            ],
            [
              -0.7464375,
              0.1069805,
              0.7820293
            ]
          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_rising",
        "violation_delay_degrade_pct": 10.0
      },
      {
        "fall_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
            2.5,
            5.0
          ],
          "index_2": [
            0.01,
            2.5,
            5.0
          ],
          "values": [
            [
              -1.0197285,
              -2.120339,
              -3.209206
            ],
            [
              -0.1296895,
              -1.2321309,
              -2.3118427
            ],
            [
              0.4831035,
              -0.6175068,
              -1.6935567
            ]
          ]
        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
            2.5,
            5.0
          ],
          "index_2": [
            0.01,
            2.5,
            5.0
          ],
          "values": [
            [
              -0.1591328,
              -1.0253682,
              -1.7059101
            ],
            [
              0.3921611,
              -0.4594258,
              -1.1234883
            ],
            [
              0.8072002,
              -0.0370625,
              -0.6956318
            ]
          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10.0
      }
    ]
  },
  "statetable,CLK GATE SCE,M0": {
    "table": [
      "L L L : - : L",
      "L L H : - : H",
      "L H L : - : H",
      "L H H : - : H",
      "H - - : - : N"
    ]
  }
}