{
  "area": 20.0192,
  "cell_footprint": "sky130_fd_sc_hdll__sdlclkp",
  "cell_leakage_power": 0.0,
  "clock_gating_integrated_cell": "latch_posedge_precontrol",
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    "pg_type": "primary_ground",
    "related_bias_pin": "VPB",
    "voltage_name": "VGND"
  },
  "pg_pin,VNB": {
    "pg_type": "nwell",
    "physical_connection": "device_layer",
    "voltage_name": "VNB"
  },
  "pg_pin,VPB": {
    "pg_type": "pwell",
    "physical_connection": "device_layer",
    "voltage_name": "VPB"
  },
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    "pg_type": "primary_power",
    "related_bias_pin": "VNB",
    "voltage_name": "VPWR"
  },
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    "clock_gate_clock_pin": "true",
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      "rise_power,power_inputs_1": {
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    "max_transition": 1.5,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.003575,
    "timing": {
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      "related_pin": "CLK",
      "sim_opt": "runlvl=5 accurate=1",
      "timing_type": "min_pulse_width",
      "violation_delay_degrade_pct": 10.0
    }
  },
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    "clock": "false",
    "clock_gate_enable_pin": "true",
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    "fall_capacitance": 0.001605,
    "internal_power": {
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      "rise_power,power_inputs_1": {
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    "max_transition": 1.5,
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        "related_pin": "CLK",
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        "sim_opt": "runlvl=5 accurate=1",
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        "violation_delay_degrade_pct": 10.0
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      {
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        "related_pin": "CLK",
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        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10.0
      }
    ]
  },
  "pin,GCLK": {
    "clock_gate_out_pin": "true",
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        "related_pin": "CLK",
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        "when": "(!GATE&SCE)"
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      {
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        "related_pin": "CLK",
        "rise_power,power_outputs_1": {
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        "when": "(GATE&!SCE)"
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      {
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        "when": "(GATE&SCE)"
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      {
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        "when": "(!GATE&!SCE)"
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    "max_capacitance": 0.078288,
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    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "state_function": "(CLK*M0)",
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            0.0011608,
            0.0026949,
            0.0062565,
            0.0145251,
            0.0337214,
            0.0782876
          ],
          "values": [
            [
              0.0355019,
              0.0416382,
              0.0522954,
              0.0764545,
              0.1304649,
              0.2573997,
              0.5742504
            ],
            [
              0.0359279,
              0.0410574,
              0.0523388,
              0.0763133,
              0.1304064,
              0.2581107,
              0.5741195
            ],
            [
              0.0355032,
              0.0409964,
              0.0523959,
              0.076273,
              0.1303358,
              0.2588983,
              0.5740768
            ],
            [
              0.0359376,
              0.0410274,
              0.0523156,
              0.0764394,
              0.1304868,
              0.2577919,
              0.5741741
            ],
            [
              0.0355724,
              0.0416977,
              0.0523342,
              0.0765666,
              0.1303304,
              0.2587979,
              0.5741206
            ],
            [
              0.0370177,
              0.0419226,
              0.0528907,
              0.076878,
              0.1306965,
              0.2579708,
              0.5742371
            ],
            [
              0.0523439,
              0.0573377,
              0.0681896,
              0.0905387,
              0.1417848,
              0.2646415,
              0.5762969
            ]
          ]
        },
        "related_pin": "CLK",
        "sdf_cond": "GATE==1'b0&&SCE==1'b0",
        "timing_sense": "positive_unate",
        "timing_type": "combinational_fall",
        "when": "(!GATE&!SCE)"
      }
    ]
  },
  "pin,M0": {
    "direction": "internal",
    "internal_node": "M0",
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR"
  },
  "pin,SCE": {
    "capacitance": 0.001705,
    "clock": "false",
    "clock_gate_test_pin": "true",
    "direction": "input",
    "fall_capacitance": 0.00159,
    "internal_power": {
      "fall_power,power_inputs_1": {
        "index_1": [
          0.01,
          0.0230506,
          0.0531329,
          0.122474,
          0.282311,
          0.650743,
          1.5
        ],
        "values": [
          0.0133605,
          0.0127431,
          0.0113202,
          0.0119462,
          0.0133892,
          0.0167153,
          0.0243824
        ]
      },
      "rise_power,power_inputs_1": {
        "index_1": [
          0.01,
          0.0230506,
          0.0531329,
          0.122474,
          0.282311,
          0.650743,
          1.5
        ],
        "values": [
          0.0152127,
          0.0152027,
          0.0151797,
          0.0151644,
          0.0151292,
          0.0150481,
          0.0148612
        ]
      }
    },
    "max_transition": 1.5,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.001821,
    "timing": [
      {
        "fall_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
            0.5,
            1.5
          ],
          "index_2": [
            0.01,
            0.5,
            1.5
          ],
          "values": [
            [
              0.3950664,
              0.5746563,
              0.9323223
            ],
            [
              0.2362285,
              0.4158184,
              0.7747051
            ],
            [
              0.0628887,
              0.2412578,
              0.5964824
            ]
          ]
        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
            0.5,
            1.5
          ],
          "index_2": [
            0.01,
            0.5,
            1.5
          ],
          "values": [
            [
              0.1655742,
              0.3183086,
              0.5416973
            ],
            [
              0.0433574,
              0.1973125,
              0.4145976
            ],
            [
              -0.0530781,
              0.0984355,
              0.3083965
            ]
          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_rising",
        "violation_delay_degrade_pct": 10.0
      },
      {
        "fall_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
            0.5,
            1.5
          ],
          "index_2": [
            0.01,
            0.5,
            1.5
          ],
          "values": [
            [
              -0.3910664,
              -0.5706563,
              -0.9295429
            ],
            [
              -0.2322285,
              -0.4105976,
              -0.7707051
            ],
            [
              -0.057668,
              -0.2372578,
              -0.5924824
            ]
          ]
        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
            0.5,
            1.5
          ],
          "index_2": [
            0.01,
            0.5,
            1.5
          ],
          "values": [
            [
              -0.088332,
              -0.2410664,
              -0.4546895
            ],
            [
              -0.0027363,
              -0.1554707,
              -0.3593281
            ],
            [
              0.0900371,
              -0.0590352,
              -0.2604512
            ]
          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10.0
      }
    ]
  },
  "statetable,CLK GATE SCE,M0": {
    "table": [
      "L L L : - : L",
      "L L H : - : H",
      "L H L : - : H",
      "L H H : - : H",
      "H - - : - : N"
    ]
  }
}