{
  "area": 20.0192,
  "cell_footprint": "sky130_fd_sc_hdll__sdlclkp",
  "cell_leakage_power": 0.0,
  "clock_gating_integrated_cell": "latch_posedge_precontrol",
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    "pg_type": "primary_ground",
    "related_bias_pin": "VPB",
    "voltage_name": "VGND"
  },
  "pg_pin,VNB": {
    "pg_type": "nwell",
    "physical_connection": "device_layer",
    "voltage_name": "VNB"
  },
  "pg_pin,VPB": {
    "pg_type": "pwell",
    "physical_connection": "device_layer",
    "voltage_name": "VPB"
  },
  "pg_pin,VPWR": {
    "pg_type": "primary_power",
    "related_bias_pin": "VNB",
    "voltage_name": "VPWR"
  },
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    "clock_gate_clock_pin": "true",
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      "rise_power,power_inputs_1": {
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    "max_transition": 5.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.003251,
    "timing": {
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      "related_pin": "CLK",
      "sim_opt": "runlvl=5 accurate=1",
      "timing_type": "min_pulse_width",
      "violation_delay_degrade_pct": 10.0
    }
  },
  "pin,GATE": {
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    "clock": "false",
    "clock_gate_enable_pin": "true",
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    "fall_capacitance": 0.001444,
    "internal_power": {
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      "rise_power,power_inputs_1": {
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    },
    "max_transition": 5.0,
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    "rise_capacitance": 0.001804,
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              1.7946025
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        "related_pin": "CLK",
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          "index_2": [
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              0.7124492
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        "sim_opt": "runlvl=5 accurate=1",
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        "violation_delay_degrade_pct": 10.0
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      {
        "fall_constraint,vio_3_3_1": {
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        },
        "related_pin": "CLK",
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            5.0
          ],
          "index_2": [
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              -0.1426533,
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              -0.6242207
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        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10.0
      }
    ]
  },
  "pin,GCLK": {
    "clock_gate_out_pin": "true",
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        "related_pin": "CLK",
        "rise_power,power_outputs_1": {
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        "when": "(!GATE&SCE)"
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      {
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        "related_pin": "CLK",
        "rise_power,power_outputs_1": {
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        "when": "(GATE&!SCE)"
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      {
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        "when": "(GATE&SCE)"
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      {
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        "when": "(!GATE&!SCE)"
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    "max_capacitance": 0.127612,
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    "power_down_function": "(!VPWR + VGND)",
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "state_function": "(CLK*M0)",
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            0.127612
          ],
          "values": [
            [
              0.0673004,
              0.0781848,
              0.0992595,
              0.1497441,
              0.2742017,
              0.5988733,
              1.4661737
            ],
            [
              0.0681892,
              0.0771463,
              0.0993502,
              0.1494655,
              0.273692,
              0.59887,
              1.4674821
            ],
            [
              0.0682186,
              0.0775,
              0.0988551,
              0.1493857,
              0.2741959,
              0.5987078,
              1.4661223
            ],
            [
              0.0680371,
              0.0770061,
              0.0991723,
              0.1493813,
              0.2742682,
              0.5987429,
              1.4675409
            ],
            [
              0.0682042,
              0.0778725,
              0.0994648,
              0.1494865,
              0.2737406,
              0.6004428,
              1.464333
            ],
            [
              0.0685332,
              0.0772919,
              0.0997977,
              0.1499923,
              0.2743639,
              0.6006478,
              1.4646293
            ],
            [
              0.1067048,
              0.1158393,
              0.1370999,
              0.1832999,
              0.2992038,
              0.6098071,
              1.4676889
            ]
          ]
        },
        "related_pin": "CLK",
        "sdf_cond": "GATE==1'b0&&SCE==1'b0",
        "timing_sense": "positive_unate",
        "timing_type": "combinational_fall",
        "when": "(!GATE&!SCE)"
      }
    ]
  },
  "pin,M0": {
    "direction": "internal",
    "internal_node": "M0",
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR"
  },
  "pin,SCE": {
    "capacitance": 0.001558,
    "clock": "false",
    "clock_gate_test_pin": "true",
    "direction": "input",
    "fall_capacitance": 0.001423,
    "internal_power": {
      "fall_power,power_inputs_1": {
        "index_1": [
          0.01,
          0.0281727,
          0.0793701,
          0.223607,
          0.629961,
          1.77477,
          4.9999998
        ],
        "values": [
          0.0047095,
          0.0045725,
          0.0041868,
          0.0045178,
          0.0054503,
          0.0080776,
          0.0154791
        ]
      },
      "rise_power,power_inputs_1": {
        "index_1": [
          0.01,
          0.0281727,
          0.0793701,
          0.223607,
          0.629961,
          1.77477,
          4.9999998
        ],
        "values": [
          0.0095682,
          0.0093066,
          0.0085696,
          0.0085995,
          0.0086839,
          0.0089214,
          0.0095908
        ]
      }
    },
    "max_transition": 5.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.001694,
    "timing": [
      {
        "fall_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
            2.5,
            5.0
          ],
          "index_2": [
            0.01,
            2.5,
            5.0
          ],
          "values": [
            [
              1.0658428,
              2.1627911,
              3.2534893
            ],
            [
              0.1812969,
              1.276414,
              2.3671123
            ],
            [
              -0.4241719,
              0.6801006,
              1.7579815
            ]
          ]
        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
            2.5,
            5.0
          ],
          "index_2": [
            0.01,
            2.5,
            5.0
          ],
          "values": [
            [
              0.2913066,
              1.1795146,
              1.8838604
            ],
            [
              -0.3295674,
              0.536668,
              1.2172099
            ],
            [
              -0.729958,
              0.12346,
              0.7966777
            ]
          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_rising",
        "violation_delay_degrade_pct": 10.0
      },
      {
        "fall_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
            2.5,
            5.0
          ],
          "index_2": [
            0.01,
            2.5,
            5.0
          ],
          "values": [
            [
              -1.0581806,
              -2.1587911,
              -3.2494893
            ],
            [
              -0.1736348,
              -1.2742451,
              -2.3594501
            ],
            [
              0.4281719,
              -0.6687764,
              -1.7539815
            ]
          ]
        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
            2.5,
            5.0
          ],
          "index_2": [
            0.01,
            2.5,
            5.0
          ],
          "values": [
            [
              -0.1591328,
              -1.0271992,
              -1.7059101
            ],
            [
              0.3848369,
              -0.46675,
              -1.1308125
            ],
            [
              0.7888897,
              -0.053542,
              -0.7121113
            ]
          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10.0
      }
    ]
  },
  "statetable,CLK GATE SCE,M0": {
    "table": [
      "L L L : - : L",
      "L L H : - : H",
      "L H L : - : H",
      "L H H : - : H",
      "H - - : - : N"
    ]
  }
}