{
  "creator": "Yosys 0.9+2406 (git sha1 46ed0db2, clang 7.0.1-8 -fPIC -Os)",
  "modules": {
    "sky130_fd_sc_hdll__and3b": {
      "attributes": {
        "top": 1,
        "src": "./cells/and3b/sky130_fd_sc_hdll__and3b.functional.v:33.1-55.10"
      },
      "ports": {
        "X": {
          "direction": "output",
          "bits": [ 2 ]
        },
        "A_N": {
          "direction": "input",
          "bits": [ 3 ]
        },
        "B": {
          "direction": "input",
          "bits": [ 4 ]
        },
        "C": {
          "direction": "input",
          "bits": [ 5 ]
        }
      },
      "cells": {
        "$and$./cells/and3b/sky130_fd_sc_hdll__and3b.functional.v:52$2": {
          "hide_name": 1,
          "type": "$and",
          "parameters": {
            "A_SIGNED": 0,
            "A_WIDTH": 1,
            "B_SIGNED": 0,
            "B_WIDTH": 1,
            "Y_WIDTH": 1
          },
          "attributes": {
            "src": "./cells/and3b/sky130_fd_sc_hdll__and3b.functional.v:52.9-52.43"
          },
          "port_directions": {
            "A": "input",
            "B": "input",
            "Y": "output"
          },
          "connections": {
            "A": [ 5 ],
            "B": [ 6 ],
            "Y": [ 7 ]
          }
        },
        "$and$./cells/and3b/sky130_fd_sc_hdll__and3b.functional.v:52$3": {
          "hide_name": 1,
          "type": "$and",
          "parameters": {
            "A_SIGNED": 0,
            "A_WIDTH": 1,
            "B_SIGNED": 0,
            "B_WIDTH": 1,
            "Y_WIDTH": 1
          },
          "attributes": {
            "src": "./cells/and3b/sky130_fd_sc_hdll__and3b.functional.v:52.9-52.43"
          },
          "port_directions": {
            "A": "input",
            "B": "input",
            "Y": "output"
          },
          "connections": {
            "A": [ 7 ],
            "B": [ 4 ],
            "Y": [ 2 ]
          }
        },
        "$not$./cells/and3b/sky130_fd_sc_hdll__and3b.functional.v:0$1": {
          "hide_name": 1,
          "type": "$not",
          "parameters": {
            "A_SIGNED": 0,
            "A_WIDTH": 1,
            "Y_WIDTH": 1
          },
          "attributes": {
            "src": "./cells/and3b/sky130_fd_sc_hdll__and3b.functional.v:0.0-0.0"
          },
          "port_directions": {
            "A": "input",
            "Y": "output"
          },
          "connections": {
            "A": [ 3 ],
            "Y": [ 6 ]
          }
        }
      },
      "netnames": {
        "$and$./cells/and3b/sky130_fd_sc_hdll__and3b.functional.v:52$2_Y": {
          "hide_name": 1,
          "bits": [ 7 ],
          "attributes": {
            "src": "./cells/and3b/sky130_fd_sc_hdll__and3b.functional.v:52.9-52.43"
          }
        },
        "A_N": {
          "hide_name": 0,
          "bits": [ 3 ],
          "attributes": {
            "src": "./cells/and3b/sky130_fd_sc_hdll__and3b.functional.v:42.12-42.15"
          }
        },
        "B": {
          "hide_name": 0,
          "bits": [ 4 ],
          "attributes": {
            "src": "./cells/and3b/sky130_fd_sc_hdll__and3b.functional.v:43.12-43.13"
          }
        },
        "C": {
          "hide_name": 0,
          "bits": [ 5 ],
          "attributes": {
            "src": "./cells/and3b/sky130_fd_sc_hdll__and3b.functional.v:44.12-44.13"
          }
        },
        "X": {
          "hide_name": 0,
          "bits": [ 2 ],
          "attributes": {
            "src": "./cells/and3b/sky130_fd_sc_hdll__and3b.functional.v:41.12-41.13"
          }
        },
        "and0_out_X": {
          "hide_name": 0,
          "bits": [ 2 ],
          "attributes": {
            "src": "./cells/and3b/sky130_fd_sc_hdll__and3b.functional.v:48.10-48.20"
          }
        },
        "not0_out": {
          "hide_name": 0,
          "bits": [ 6 ],
          "attributes": {
            "src": "./cells/and3b/sky130_fd_sc_hdll__and3b.functional.v:47.10-47.18"
          }
        }
      }
    }
  }
}