blob: 7e152abaabc9b0e4e41c66a41fe3db0c26daddeb [file] [log] [blame]
{
"area": 21.2704,
"cell_footprint": "sdlclkp",
"cell_leakage_power": 7.152074,
"clock_gating_integrated_cell": "latch_posedge_precontrol",
"leakage_power": [
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"value": 8.87008,
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},
{
"value": 5.81486,
"when": "!CLK&GATE&!GCLK&!SCE"
},
{
"value": 5.82362,
"when": "!CLK&!GATE&!GCLK&SCE"
},
{
"value": 5.86603,
"when": "CLK&!GATE&GCLK&SCE"
},
{
"value": 5.33207,
"when": "!CLK&GATE&!GCLK&SCE"
},
{
"value": 7.60284,
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},
{
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"when": "CLK&GATE&GCLK&!SCE"
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{
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"when": "CLK&GATE&GCLK&SCE"
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{
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{
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"when": "CLK&!GATE&!GCLK&SCE"
},
{
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},
{
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}
],
"pg_pin VGND": {
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"related_bias_pin": "VNB",
"voltage_name": "VGND"
},
"pg_pin VNB": {
"pg_type": "pwell",
"voltage_name": "VNB"
},
"pg_pin VPB": {
"pg_type": "nwell",
"voltage_name": "VPB"
},
"pg_pin VPWR": {
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"related_bias_pin": "VPB",
"voltage_name": "VPWR"
},
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"clock": "true",
"clock_gate_clock_pin": "true",
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0.0531329,
0.122474,
0.282311,
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}
},
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"clock": "false",
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0.4097148
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0.1838848
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0.2424785
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{
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1.5
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[
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-0.3971699
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0.5,
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0.01,
0.5,
1.5
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-0.1237324
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},
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}
]
},
"pin GCLK": {
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0.122474,
0.282311,
0.650743,
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{
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{
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"state_function": "(CLK*M0)",
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]
},
"related_pin": "CLK",
"rise_constraint vio_3_3_1": {
"index_1": [
0.01,
0.5,
1.5
],
"index_2": [
0.01,
0.5,
1.5
],
"values": [
[
-0.0565937,
-0.1409688,
-0.1897969
],
[
-0.0308125,
-0.1078633,
-0.1530293
],
[
-0.0417988,
-0.1188496,
-0.1627949
]
]
},
"sim_opt": "runlvl=5 accurate=1",
"timing_type": "hold_rising",
"violation_delay_degrade_pct": 10.0
}
]
},
"statetable \"CLK GATE SCE\",\"M0\"": {
"table": "L L L : - : L ,L L H : - : H ,L H L : - : H ,L H H : - : H ,H - - : - : N"
}
}