| { | |
| "area": 11.2608, | |
| "cell_footprint": "o221a", | |
| "cell_leakage_power": 0.0, | |
| "pg_pin VGND": { | |
| "pg_type": "primary_ground", | |
| "related_bias_pin": "VNB", | |
| "voltage_name": "VGND" | |
| }, | |
| "pg_pin VNB": { | |
| "pg_type": "pwell", | |
| "voltage_name": "VNB" | |
| }, | |
| "pg_pin VPB": { | |
| "pg_type": "nwell", | |
| "voltage_name": "VPB" | |
| }, | |
| "pg_pin VPWR": { | |
| "pg_type": "primary_power", | |
| "related_bias_pin": "VPB", | |
| "voltage_name": "VPWR" | |
| }, | |
| "pin A1": { | |
| "capacitance": 0.002096, | |
| "clock": "false", | |
| "direction": "input", | |
| "fall_capacitance": 0.001992, | |
| "internal_power": { | |
| "fall_power power_inputs_1": { | |
| "index_1": [ | |
| 0.01, | |
| 0.0281727, | |
| 0.0793701, | |
| 0.223607, | |
| 0.629961, | |
| 1.77477, | |
| 4.9999998 | |
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| 0.0025551, | |
| 0.00253, | |
| 0.0025317, | |
| 0.0025367, | |
| 0.0025506, | |
| 0.0025898 | |
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| }, | |
| "rise_power power_inputs_1": { | |
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| 0.01, | |
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| 0.0793701, | |
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| }, | |
| "max_transition": 5.0, | |
| "related_ground_pin": "VGND", | |
| "related_power_pin": "VPWR", | |
| "rise_capacitance": 0.0022 | |
| }, | |
| "pin A2": { | |
| "capacitance": 0.00214, | |
| "clock": "false", | |
| "direction": "input", | |
| "fall_capacitance": 0.002022, | |
| "internal_power": { | |
| "fall_power power_inputs_1": { | |
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| 0.01, | |
| 0.0281727, | |
| 0.0793701, | |
| 0.223607, | |
| 0.629961, | |
| 1.77477, | |
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| 0.0024658, | |
| 0.0024281 | |
| ] | |
| }, | |
| "rise_power power_inputs_1": { | |
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| 0.01, | |
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| 0.0793701, | |
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| 0.629961, | |
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| }, | |
| "max_transition": 5.0, | |
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| "related_power_pin": "VPWR", | |
| "rise_capacitance": 0.002259 | |
| }, | |
| "pin B1": { | |
| "capacitance": 0.002114, | |
| "clock": "false", | |
| "direction": "input", | |
| "fall_capacitance": 0.002025, | |
| "internal_power": { | |
| "fall_power power_inputs_1": { | |
| "index_1": [ | |
| 0.01, | |
| 0.0281727, | |
| 0.0793701, | |
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| "rise_power power_inputs_1": { | |
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| }, | |
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| "related_ground_pin": "VGND", | |
| "related_power_pin": "VPWR", | |
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| }, | |
| "pin B2": { | |
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| "clock": "false", | |
| "direction": "input", | |
| "fall_capacitance": 0.002021, | |
| "internal_power": { | |
| "fall_power power_inputs_1": { | |
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| 0.01, | |
| 0.0281727, | |
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| 0.223607, | |
| 0.629961, | |
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| }, | |
| "rise_power power_inputs_1": { | |
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| }, | |
| "max_transition": 5.0, | |
| "related_ground_pin": "VGND", | |
| "related_power_pin": "VPWR", | |
| "rise_capacitance": 0.002226 | |
| }, | |
| "pin C1": { | |
| "capacitance": 0.00207, | |
| "clock": "false", | |
| "direction": "input", | |
| "fall_capacitance": 0.001962, | |
| "internal_power": { | |
| "fall_power power_inputs_1": { | |
| "index_1": [ | |
| 0.01, | |
| 0.0281727, | |
| 0.0793701, | |
| 0.223607, | |
| 0.629961, | |
| 1.77477, | |
| 4.9999998 | |
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| 0.0029342, | |
| 0.0029429 | |
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| }, | |
| "rise_power power_inputs_1": { | |
| "index_1": [ | |
| 0.01, | |
| 0.0281727, | |
| 0.0793701, | |
| 0.223607, | |
| 0.629961, | |
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| } | |
| }, | |
| "max_transition": 5.0, | |
| "related_ground_pin": "VGND", | |
| "related_power_pin": "VPWR", | |
| "rise_capacitance": 0.002178 | |
| }, | |
| "pin X": { | |
| "direction": "output", | |
| "function": "(A1&B1&C1) | (A2&B1&C1) | (A1&B2&C1) | (A2&B2&C1)", | |
| "internal_power": [ | |
| { | |
| "fall_power power_outputs_1": { | |
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| 0.0281727, | |
| 0.0793701, | |
| 0.223607, | |
| 0.629961, | |
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| [ | |
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| [ | |
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| [ | |
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| [ | |
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| [ | |
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| ] | |
| }, | |
| "related_pin": "A1", | |
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| ] | |
| }, | |
| "when": "(!A2&!B1&B2&C1)" | |
| }, | |
| { | |
| "fall_power power_outputs_1": { | |
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| ] | |
| }, | |
| "related_pin": "A1", | |
| "rise_power power_outputs_1": { | |
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| }, | |
| "when": "(!A2&B1&!B2&C1)" | |
| }, | |
| { | |
| "fall_power power_outputs_1": { | |
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| 0.01, | |
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| }, | |
| "related_pin": "A1", | |
| "rise_power power_outputs_1": { | |
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