| { |
| "area": 11.2608, |
| "cell_footprint": "mux2", |
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| "leakage_power": [ |
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| }, |
| { |
| "value": 0.07887, |
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| }, |
| { |
| "value": 0.002561, |
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| }, |
| { |
| "value": 0.0052831, |
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| }, |
| { |
| "value": 0.0059766, |
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| }, |
| { |
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| { |
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| }, |
| { |
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| ], |
| "pg_pin VGND": { |
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| "related_bias_pin": "VNB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin VNB": { |
| "pg_type": "pwell", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin VPB": { |
| "pg_type": "nwell", |
| "voltage_name": "VPB" |
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| "voltage_name": "VPWR" |
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| 0.01, |
| 0.0230506, |
| 0.0531329, |
| 0.122474, |
| 0.282311, |
| 0.650743, |
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| 0.0145443 |
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| }, |
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| "related_power_pin": "VPWR", |
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| }, |
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| "clock": "false", |
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| "internal_power": { |
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| "rise_power power_inputs_1": { |
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| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.012681 |
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| "pin X": { |
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| }, |
| "related_pin": "A1", |
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| { |
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| "related_pin": "S", |
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| }, |
| { |
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| 0.01, |
| 0.0230506, |
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| [ |
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| }, |
| "related_pin": "A0", |
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| } |
| ], |
| "max_capacitance": 0.948954, |
| "max_transition": 1.503829, |
| "power_down_function": "(!VPWR + VGND)", |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "timing": [ |
| { |
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