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  "cell_footprint": "clkinv",
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  "pg_pin VGND": {
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    "related_bias_pin": "VNB",
    "voltage_name": "VGND"
  },
  "pg_pin VNB": {
    "pg_type": "pwell",
    "voltage_name": "VNB"
  },
  "pg_pin VPB": {
    "pg_type": "nwell",
    "voltage_name": "VPB"
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  "pg_pin VPWR": {
    "pg_type": "primary_power",
    "related_bias_pin": "VPB",
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    "clock": "false",
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    "max_transition": 5.0,
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    "related_power_pin": "VPWR",
    "rise_capacitance": 0.004944
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  "pin Y": {
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    "function": "(!A)",
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    "max_capacitance": 0.355349,
    "max_transition": 5.025958,
    "power_down_function": "(!VPWR + VGND)",
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "timing": {
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      "fall_transition del_1_7_7": {
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      "timing_sense": "negative_unate",
      "timing_type": "combinational"
    }
  }
}