{
  "area": 12.512,
  "cell_footprint": "and3",
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  "pg_pin VGND": {
    "pg_type": "primary_ground",
    "related_bias_pin": "VNB",
    "voltage_name": "VGND"
  },
  "pg_pin VNB": {
    "pg_type": "pwell",
    "voltage_name": "VNB"
  },
  "pg_pin VPB": {
    "pg_type": "nwell",
    "voltage_name": "VPB"
  },
  "pg_pin VPWR": {
    "pg_type": "primary_power",
    "related_bias_pin": "VPB",
    "voltage_name": "VPWR"
  },
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    "clock": "false",
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      "rise_power power_inputs_1": {
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    "max_transition": 1.5,
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    "related_power_pin": "VPWR",
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  "pin B": {
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    "clock": "false",
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    "internal_power": {
      "fall_power power_inputs_1": {
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      "rise_power power_inputs_1": {
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    "max_transition": 1.5,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.002432
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  "pin C": {
    "capacitance": 0.002327,
    "clock": "false",
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    "internal_power": {
      "fall_power power_inputs_1": {
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          0.650743,
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        "values": [
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      "rise_power power_inputs_1": {
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    "max_transition": 1.5,
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      {
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    "related_ground_pin": "VGND",
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    "timing": [
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