{ | |
"area": 12.512, | |
"cell_footprint": "a32o", | |
"cell_leakage_power": 0.0, | |
"pg_pin VGND": { | |
"pg_type": "primary_ground", | |
"related_bias_pin": "VNB", | |
"voltage_name": "VGND" | |
}, | |
"pg_pin VNB": { | |
"pg_type": "pwell", | |
"voltage_name": "VNB" | |
}, | |
"pg_pin VPB": { | |
"pg_type": "nwell", | |
"voltage_name": "VPB" | |
}, | |
"pg_pin VPWR": { | |
"pg_type": "primary_power", | |
"related_bias_pin": "VPB", | |
"voltage_name": "VPWR" | |
}, | |
"pin A1": { | |
"capacitance": 0.002003, | |
"clock": "false", | |
"direction": "input", | |
"fall_capacitance": 0.001957, | |
"internal_power": { | |
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"index_1": [ | |
0.01, | |
0.0281727, | |
0.0793701, | |
0.223607, | |
0.629961, | |
1.77477, | |
4.9999998 | |
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0.0020468, | |
0.0020585, | |
0.002051, | |
0.0020297, | |
0.0019697, | |
0.0018006 | |
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0.01, | |
0.0281727, | |
0.0793701, | |
0.223607, | |
0.629961, | |
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-0.0016408, | |
-0.0016002, | |
-0.0014857 | |
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}, | |
"max_transition": 5.0, | |
"related_ground_pin": "VGND", | |
"related_power_pin": "VPWR", | |
"rise_capacitance": 0.00205 | |
}, | |
"pin A2": { | |
"capacitance": 0.002011, | |
"clock": "false", | |
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"internal_power": { | |
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0.01, | |
0.0281727, | |
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0.0017547, | |
0.001775 | |
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0.01, | |
0.0281727, | |
0.0793701, | |
0.223607, | |
0.629961, | |
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-0.0017242, | |
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}, | |
"pin A3": { | |
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"clock": "false", | |
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"index_1": [ | |
0.01, | |
0.0281727, | |
0.0793701, | |
0.223607, | |
0.629961, | |
1.77477, | |
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0.0017948, | |
0.0017959, | |
0.0017914, | |
0.0017788, | |
0.0017431, | |
0.0016426 | |
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}, | |
"rise_power power_inputs_1": { | |
"index_1": [ | |
0.01, | |
0.0281727, | |
0.0793701, | |
0.223607, | |
0.629961, | |
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-0.0017823, | |
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-0.0017866, | |
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"rise_capacitance": 0.002021 | |
}, | |
"pin B1": { | |
"capacitance": 0.001982, | |
"clock": "false", | |
"direction": "input", | |
"fall_capacitance": 0.001913, | |
"internal_power": { | |
"fall_power power_inputs_1": { | |
"index_1": [ | |
0.01, | |
0.0281727, | |
0.0793701, | |
0.223607, | |
0.629961, | |
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0.0020997, | |
0.0020798, | |
0.0020807, | |
0.0020833, | |
0.0020906, | |
0.002111 | |
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"rise_power power_inputs_1": { | |
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0.01, | |
0.0281727, | |
0.0793701, | |
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0.629961, | |
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-0.001808, | |
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-0.0016897 | |
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}, | |
"max_transition": 5.0, | |
"related_ground_pin": "VGND", | |
"related_power_pin": "VPWR", | |
"rise_capacitance": 0.002051 | |
}, | |
"pin B2": { | |
"capacitance": 0.002096, | |
"clock": "false", | |
"direction": "input", | |
"fall_capacitance": 0.002009, | |
"internal_power": { | |
"fall_power power_inputs_1": { | |
"index_1": [ | |
0.01, | |
0.0281727, | |
0.0793701, | |
0.223607, | |
0.629961, | |
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0.0020621, | |
0.002057, | |
0.002057, | |
0.0020572, | |
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0.0020591 | |
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}, | |
"rise_power power_inputs_1": { | |
"index_1": [ | |
0.01, | |
0.0281727, | |
0.0793701, | |
0.223607, | |
0.629961, | |
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"values": [ | |
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-0.0020604, | |
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}, | |
"max_transition": 5.0, | |
"related_ground_pin": "VGND", | |
"related_power_pin": "VPWR", | |
"rise_capacitance": 0.002184 | |
}, | |
"pin X": { | |
"direction": "output", | |
"function": "(A1&A2&A3) | (B1&B2)", | |
"internal_power": [ | |
{ | |
"fall_power power_outputs_1": { | |
"index_1": [ | |
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0.629961, | |
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5 | |
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0.0191438, | |
0.04762035, | |
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[ | |
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0.0074926, | |
0.0062177, | |
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[ | |
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[ | |
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0.0281727, | |
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5 | |
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[ | |
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[ | |
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[ | |
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[ | |
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[ | |
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[ | |
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0.0148034, | |
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0.0474301, | |
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"when": "(A2&A3&!B1&!B2)" | |
}, | |
{ | |
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0.0281727, | |
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0.629961, | |
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[ | |
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[ | |
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[ | |
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[ | |
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[ | |
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0.0281727, | |
0.0793701, | |
0.223607, | |
0.629961, | |
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5 | |
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0.0095943, | |
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0.0479686, | |
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[ | |
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0.009581, | |
0.011176, | |
0.0150541, | |
0.0244336, | |
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[ | |
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[ | |
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[ | |
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[ | |
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[ | |
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0.0108036, | |
0.0144954, | |
0.0238939, | |
0.0472842, | |
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}, | |
"when": "(A2&A3&!B1&B2)" | |
}, | |
{ | |
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0.0281727, | |
0.0793701, | |
0.223607, | |
0.629961, | |
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5 | |
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[ | |
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[ | |
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[ | |
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0.0281727, | |
0.0793701, | |
0.223607, | |
0.629961, | |
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[ | |
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[ | |
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[ | |
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[ | |
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[ | |
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[ | |
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0.0239972, | |
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}, | |
{ | |
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0.0281727, | |
0.0793701, | |
0.223607, | |
0.629961, | |
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5 | |
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[ | |
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