| { |
| "area": 7.5072, |
| "cell_footprint": "a211oi", |
| "cell_leakage_power": 0.8773488, |
| "leakage_power": [ |
| { |
| "value": 0.966964, |
| "when": "!A1&!A2&!B1&C1" |
| }, |
| { |
| "value": 1.81662, |
| "when": "!A1&!A2&!B1&!C1" |
| }, |
| { |
| "value": 0.14959, |
| "when": "!A1&!A2&B1&C1" |
| }, |
| { |
| "value": 0.543423, |
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| }, |
| { |
| "value": 0.96694, |
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| }, |
| { |
| "value": 2.69446, |
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| }, |
| { |
| "value": 0.149589, |
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| }, |
| { |
| "value": 0.543416, |
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| }, |
| { |
| "value": 0.966934, |
| "when": "A1&!A2&!B1&C1" |
| }, |
| { |
| "value": 2.3628, |
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| }, |
| { |
| "value": 0.149589, |
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| }, |
| { |
| "value": 0.543414, |
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| }, |
| { |
| "value": 0.3382, |
| "when": "A1&A2&!B1&C1" |
| }, |
| { |
| "value": 1.45872, |
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| { |
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| }, |
| { |
| "value": 0.269246, |
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| ], |
| "pg_pin VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin VNB": { |
| "pg_type": "pwell", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin VPB": { |
| "pg_type": "nwell", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin VPWR": { |
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| "related_bias_pin": "VPB", |
| "voltage_name": "VPWR" |
| }, |
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| "clock": "false", |
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| 0.01, |
| 0.0230506, |
| 0.0531329, |
| 0.122474, |
| 0.282311, |
| 0.650743, |
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| "related_power_pin": "VPWR", |
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| }, |
| "pin A2": { |
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| "clock": "false", |
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| 0.0032367 |
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| "related_power_pin": "VPWR", |
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| }, |
| "pin B1": { |
| "capacitance": 0.002512, |
| "clock": "false", |
| "direction": "input", |
| "fall_capacitance": 0.002336, |
| "internal_power": { |
| "fall_power power_inputs_1": { |
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| 0.0531329, |
| 0.122474, |
| 0.282311, |
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| }, |
| "rise_power power_inputs_1": { |
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| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.002688 |
| }, |
| "pin C1": { |
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| "clock": "false", |
| "direction": "input", |
| "fall_capacitance": 0.002181, |
| "internal_power": { |
| "fall_power power_inputs_1": { |
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| 0.01, |
| 0.0230506, |
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| 0.122474, |
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| }, |
| "rise_power power_inputs_1": { |
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| }, |
| "max_transition": 1.5, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.002623 |
| }, |
| "pin Y": { |
| "direction": "output", |
| "function": "(!A1&!B1&!C1) | (!A2&!B1&!C1)", |
| "internal_power": [ |
| { |
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| [ |
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| [ |
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| ] |
| }, |
| "related_pin": "A1", |
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| 0.01, |
| 0.0230506, |
| 0.0531329, |
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| 0.0213201, |
| 0.0325826, |
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| ] |
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| "when": "(A2&!B1&!C1)" |
| }, |
| { |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| ] |
| }, |
| "related_pin": "A2", |
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| 0.0230506, |
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| [ |
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| 0.0359244, |
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| ] |
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| }, |
| { |
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| 0.01, |
| 0.0230506, |
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| }, |
| "related_pin": "B1", |
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| { |
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