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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__UDP_DFF_PR_V
`define SKY130_FD_SC_HDLL__UDP_DFF_PR_V
/**
* udp_dff$PR: Positive edge triggered D flip-flop with active high
*
* Verilog primitive definition.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef NO_PRIMITIVES
`include "./sky130_fd_sc_hdll__udp_dff_pr.blackbox.v"
`else
primitive sky130_fd_sc_hdll__udp_dff$PR (
Q ,
D ,
CLK ,
RESET
);
output Q ;
input D ;
input CLK ;
input RESET;
reg Q;
table
// D CLK RESET : Qt : Qt+1
* b 0 : ? : - ; // data event, hold unless CP==x
? (?0) 0 : ? : - ; // CP => 0, hold
? b (?0) : ? : - ; // R => 0, hold unless CP==x
? ? 1 : ? : 0 ; // async reset
0 r ? : ? : 0 ; // clock data on CP
1 r 0 : ? : 1 ; // clock data on CP
0 (x1) ? : 0 : 0 ; // possible CP, hold when D==Q==0
1 (x1) 0 : 1 : 1 ; // possible CP, hold when D==Q==1
0 x ? : 0 : 0 ; // unkown CP, hold when D==Q==0
1 x 0 : 1 : 1 ; // unkown CP, hold when D==Q==1
? b (?x) : 0 : 0 ; // R=>x, hold when Q==0 unless CP==x
endtable
endprimitive
`endif // NO_PRIMITIVES
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__UDP_DFF_PR_V