| { |
| "area": 13.7632, |
| "cell_footprint": "clkmux2", |
| "cell_leakage_power": 0.0001303138, |
| "leakage_power": [ |
| { |
| "value": 0.0001131, |
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| }, |
| { |
| "value": 0.0001139, |
| "when": "!A0&!A1&!S" |
| }, |
| { |
| "value": 0.0001048, |
| "when": "!A0&A1&S" |
| }, |
| { |
| "value": 0.0001437, |
| "when": "!A0&A1&!S" |
| }, |
| { |
| "value": 0.0001391, |
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| }, |
| { |
| "value": 0.000216, |
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| }, |
| { |
| "value": 0.0001051, |
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| }, |
| { |
| "value": 0.0001069, |
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| } |
| ], |
| "pg_pin VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin VNB": { |
| "pg_type": "pwell", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin VPB": { |
| "pg_type": "nwell", |
| "voltage_name": "VPB" |
| }, |
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| "pg_type": "primary_power", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VPWR" |
| }, |
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| "clock": "false", |
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| "fall_capacitance": 0.001753, |
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| 0.01, |
| 0.0281727, |
| 0.0793701, |
| 0.223607, |
| 0.629961, |
| 1.77477, |
| 4.9999998 |
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| 0.001665, |
| 0.0016676, |
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| 0.0016958, |
| 0.0017543 |
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| }, |
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| }, |
| "max_transition": 5.0, |
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| "related_power_pin": "VPWR", |
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| }, |
| "pin A1": { |
| "capacitance": 0.00213, |
| "clock": "false", |
| "direction": "input", |
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| "internal_power": { |
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| 0.0281727, |
| 0.0793701, |
| 0.223607, |
| 0.629961, |
| 1.77477, |
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| }, |
| "rise_power power_inputs_1": { |
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| }, |
| "max_transition": 5.0, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.002217 |
| }, |
| "pin S": { |
| "capacitance": 0.003911, |
| "clock": "false", |
| "direction": "input", |
| "fall_capacitance": 0.003736, |
| "internal_power": { |
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| 0.01, |
| 0.0281727, |
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| 0.0071755, |
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| 0.0071551, |
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| }, |
| "rise_power power_inputs_1": { |
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| 0.01, |
| 0.0281727, |
| 0.0793701, |
| 0.223607, |
| 0.629961, |
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| }, |
| "max_transition": 5.0, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.004085 |
| }, |
| "pin X": { |
| "direction": "output", |
| "function": "(A0&!S) | (A1&S)", |
| "internal_power": [ |
| { |
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| ] |
| }, |
| "related_pin": "A0", |
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| 0.01, |
| 0.0281727, |
| 0.0793701, |
| 0.223607, |
| 0.629961, |
| 1.77477, |
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| }, |
| { |
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| 0.0281727, |
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| [ |
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| [ |
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| [ |
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| }, |
| "related_pin": "A1", |
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| 0.01, |
| 0.0281727, |
| 0.0793701, |
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| 1.77477, |
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| [ |
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| }, |
| { |
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| 0.01, |
| 0.0281727, |
| 0.0793701, |
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| 0.629961, |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| ] |
| }, |
| "related_pin": "S", |
| "rise_power power_outputs_1": { |
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| 0.01, |
| 0.0281727, |
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| 0.223607, |
| 0.629961, |
| 1.77477, |
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| [ |
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| [ |
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| [ |
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| } |
| } |
| ], |
| "max_capacitance": 0.103579, |
| "max_transition": 5.004169, |
| "power_down_function": "(!VPWR + VGND)", |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "timing": [ |
| { |
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| 0.01, |
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