{
  "area": 21.2704,
  "cell_footprint": "sky130_fd_sc_hdll__sdlclkp",
  "cell_leakage_power": 0.0,
  "clock_gating_integrated_cell": "latch_posedge_precontrol",
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    "pg_type": "primary_ground",
    "related_bias_pin": "VPB",
    "voltage_name": "VGND"
  },
  "pg_pin,VNB": {
    "pg_type": "nwell",
    "physical_connection": "device_layer",
    "voltage_name": "VNB"
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    "physical_connection": "device_layer",
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    "related_bias_pin": "VNB",
    "voltage_name": "VPWR"
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    "clock_gate_clock_pin": "true",
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    "max_transition": 1.5,
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      "sim_opt": "runlvl=5 accurate=1",
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      "violation_delay_degrade_pct": 10.0
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    "clock_gate_enable_pin": "true",
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        "sim_opt": "runlvl=5 accurate=1",
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        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10.0
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    ]
  },
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    "clock_gate_out_pin": "true",
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        "when": "(!GATE&SCE)"
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      {
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        "when": "(GATE&!SCE)"
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      {
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      {
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    "related_power_pin": "VPWR",
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            0.650743,
            1.5
          ],
          "index_2": [
            0.0005,
            0.0012962,
            0.0033602,
            0.0087109,
            0.0225819,
            0.0585406,
            0.151759
          ],
          "values": [
            [
              0.043194,
              0.0469799,
              0.0559819,
              0.0767029,
              0.1232099,
              0.2373685,
              0.5522473
            ],
            [
              0.0433729,
              0.0472135,
              0.0560517,
              0.0761396,
              0.1230865,
              0.2373495,
              0.5530771
            ],
            [
              0.043343,
              0.0471655,
              0.056013,
              0.0764828,
              0.1232125,
              0.2371805,
              0.5522546
            ],
            [
              0.0431878,
              0.0473032,
              0.0560757,
              0.0768977,
              0.1229943,
              0.2367144,
              0.5531196
            ],
            [
              0.0434012,
              0.0470348,
              0.056068,
              0.0766084,
              0.1232233,
              0.2372441,
              0.5521441
            ],
            [
              0.0432937,
              0.0474296,
              0.056632,
              0.0762829,
              0.1236467,
              0.2370011,
              0.5528733
            ],
            [
              0.0567911,
              0.0605345,
              0.0694002,
              0.0886804,
              0.1308104,
              0.2423983,
              0.5528293
            ]
          ]
        },
        "related_pin": "CLK",
        "sdf_cond": "GATE==1'b0&&SCE==1'b0",
        "timing_sense": "positive_unate",
        "timing_type": "combinational_fall",
        "when": "(!GATE&!SCE)"
      }
    ]
  },
  "pin,M0": {
    "direction": "internal",
    "internal_node": "M0",
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR"
  },
  "pin,SCE": {
    "capacitance": 0.001707,
    "clock": "false",
    "clock_gate_test_pin": "true",
    "direction": "input",
    "fall_capacitance": 0.001591,
    "internal_power": {
      "fall_power,power_inputs_1": {
        "index_1": [
          0.01,
          0.0230506,
          0.0531329,
          0.122474,
          0.282311,
          0.650743,
          1.5
        ],
        "values": [
          0.0133248,
          0.0127152,
          0.0113101,
          0.0119479,
          0.0134183,
          0.0168074,
          0.0246197
        ]
      },
      "rise_power,power_inputs_1": {
        "index_1": [
          0.01,
          0.0230506,
          0.0531329,
          0.122474,
          0.282311,
          0.650743,
          1.5
        ],
        "values": [
          0.0153328,
          0.0153235,
          0.0153021,
          0.0152633,
          0.0151738,
          0.0149675,
          0.0144919
        ]
      }
    },
    "max_transition": 1.5,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.001822,
    "timing": [
      {
        "fall_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
            0.5,
            1.5
          ],
          "index_2": [
            0.01,
            0.5,
            1.5
          ],
          "values": [
            [
              0.392625,
              0.5722148,
              0.9311016
            ],
            [
              0.2337871,
              0.4121562,
              0.771043
            ],
            [
              0.0555645,
              0.2351543,
              0.5891582
            ]
          ]
        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
            0.5,
            1.5
          ],
          "index_2": [
            0.01,
            0.5,
            1.5
          ],
          "values": [
            [
              0.1936504,
              0.3476055,
              0.5697734
            ],
            [
              0.0555645,
              0.2095195,
              0.4280254
            ],
            [
              -0.0530781,
              0.0984355,
              0.3071758
            ]
          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_rising",
        "violation_delay_degrade_pct": 10.0
      },
      {
        "fall_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
            0.5,
            1.5
          ],
          "index_2": [
            0.01,
            0.5,
            1.5
          ],
          "values": [
            [
              -0.3776387,
              -0.5572285,
              -0.9148945
            ],
            [
              -0.2224629,
              -0.3996113,
              -0.7597187
            ],
            [
              -0.0454609,
              -0.2250508,
              -0.5790547
            ]
          ]
        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
            0.5,
            1.5
          ],
          "index_2": [
            0.01,
            0.5,
            1.5
          ],
          "values": [
            [
              -0.088332,
              -0.2410664,
              -0.4546895
            ],
            [
              -0.0015156,
              -0.15425,
              -0.3568867
            ],
            [
              0.0949199,
              -0.055373,
              -0.2567891
            ]
          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10.0
      }
    ]
  },
  "statetable,CLK GATE SCE,M0": {
    "table": [
      "L L L : - : L",
      "L L H : - : H",
      "L H L : - : H",
      "L H H : - : H",
      "H - - : - : N"
    ]
  }
}